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Part Number: ADC12J1600
I am using the ADC12J1600 to digitize a chirp signal. I have configured the ADC and connected it to TSW14J10 (through FMC connector) and to KC705 Xilinx FPGA. When I launch the HSDC pro, it reads the TSW correctly. However, in the dropdown for ADC, I don't see an option for ADC12J1600.
Q1. How do I add that? I tried exporting settings from ADC12J1600EVM GUI and copy it there. But it is a register file and not .ini file and hence does not work.
When I try to download firmware from HSDC to FPGA, I select TSW14J10_KC705.svf but it puts out a dialog box and does not configure the FPGA.
Could you please guide me to proceed?
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In reply to Jim Brinkhurst1:
I am using theTSW14J10 interposer card. The FPGA board is the KC705. I selected the firmware from this location -> C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\14J10KC705 Details\Firmware
But somehow it appears as ZC706 in the pop-up.
I have connected the TSW to HPC FMC port of FPGA. Is that ok? Also, I have set the jumpers J2 adn J5 on TSW on 2-3 so that JTAG is through FMC. I was tryin both JTAG options and hence te JTAG ribbon in the picture.
Here is my setup picture
In reply to Mahesh K C47:
Thank you for the quick response.
I see what you are saying. When I plug in the USB and launch HSDC pro, it shows only this device to connect to which says ZC706. Is there some setting that I need to change?
On the TSW14J10EVM, make sure the jumpers are set as follows:
JP2-JP5 pins 1-2
JP6 pins 2-3
On dipswitch SW5, only switch 2 should be set to the "ON" position.
Make sure on the ADC12J1600EVM, there is a shunt on the jumper labeled as "KC705 JTAG". This is located near the FMC connector.
In reply to jim s:
With ADC12J1600EVM and KC705 (max 4 SERDES lanes) the highest bandwidth available will be in the following configuration:
You would use the HSDC Pro device file ADC12J4000_DEC_4.
Configure with output sample rate = 400M samples/sec.
The FPGA clock frequencies may need to be adjusted for the Xilinx capture board.
In the ADC12J1600EVM GUI navigate to the Low Level View tab.
The registers to adjust are:
The default value at LMK04828 register 0x110 after configuring the board will be 8. Change the Write Data value to 4 and then click Write Register.
At this point the ADC EVM should be outputting the proper data and clocks to allow the KC705 to load firmware, initialize and capture data.
You are amazing. I tried this and it works. Thank you so much.
I am trying to understand the output framing. In this output data diagram for my chosen configuration, shouldn't I0, I1, Q0.... be 12 bits? The frame is of 16 bits as it has 2 octets implies I0 = 16bits. Or is it that the control/tail bits are not shown?
Is this data rate at 1600/4 * 2 * 5/4 = 1Gsps? Or is it just 400Msps? Does that mean the clock is 400MHz at the output?
I can set my input signal to repeat at ~500KHz and I need 1000 samples per repetition => 500Msps data rate. Is 400Msps the highest I can get from this setup?
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