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ADS7883: Mismatch between ADS7883 datasheet and performance on a developed board

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Replies: 5

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Part Number: ADS7883

SPI signals which I sampled from ADS7883 component in my board, are attached above.

Above the signals there is a ruler with numerated ticks.

The time between each two adjacent ticks is 1/75Mhz. The SCLK is spread over 5 ticks. So it means that SCLK frequency that I use is 15Mhz.

I don't understand 3 things:

1. According to the datasheet ADS7883 is supposed to output on its SDA output 16 bits on each reading cycle.

    According to the datasheet the first 2 bits (of the 16 bits) are always zero

    So why is the first bit = ‘1’ on each reading cycle (as seen in the sampled signals above)?

 

2. According to the datasheet the last 2 bits (of the 16 bits) are always zero.

    So why is one of the 2 last bits on each reading cycle (as seen in the sampled signals above) different from ‘0’?

 

3. Why do I get the short zero on SDA signal on tick number 1722?

    I don’t understand how the data (of SDA) can be shorter than the SCLK.

 

Waiting for answers

Regards

Zvi

  • Hello Zvi,

    The waveforms you recorded are definitely not expected.

    Can you capture the waveforms for /CS, SCLK, SDO using a scope, verses the logic analyzer? It is possible there is a lot of noise, or slow rise and fall times, that are violating the timing specifications.

    Regards,
    Keith N.
    Precision ADC Applications
  • Hello Zvi,

    What is the Vdd you are using?

    1. In normal mode of operation the device should output a 0 on SDO with the falling edge of chip select. This is a good indicator of if the result is in good working condition, if this first zero at the CS falling edge does not appear then right away you know something is not operating correctly. Your SDO results do not seem to be consistent, the best way to debug the issue is use a DC known input, this way you know what your output should be.
    2. Your understanding is correct, the last two bits should be zero as well. From the looks of it, I suspect there is a timing error due to the shortened end bit between markers 1712 and 1728. It is acceptable for the first output bit is shortened but all bits following should be the same length. From your image, it seems that one gets cut short as something drives SDO up before the entire bit is clocked out.
    3. You are on the correct path, this shortened bit is a good indicator that something is not operating corectly.

    I would suggest debugging using a known DC input, this way you will know what to expect your output to be and be sure that the device is in normal operation mode. I would also double check your timing, to make sure that the clock frequency and CS frequency is correct and within operating conditions of the device. From your image, it almost looks like the sclk pulses are not equivalent, although it is not explicetly stated, please make sure the sclk high pulse = low pulse. Also make sure that there is nothing else driving your output line.


    Regards
    Cynthia
  • In reply to Cynthia:

    • In my board Vdd=5V.

    • The SCLK siganl in my board is not 50% duty cycle.

               I will change the SCLK duty cycle to 50% as suggested.

    • About using a DC value as an input to the ADS7883, for confirming consistency between different readigs of the ADS7883: I will try it.

    Regards

    Zvi

  • In reply to Zvi Biener:

    Reply for ADS7883: Mismatch between ADS7883 datasheet and performance on a developed board
  • In reply to Zvi Biener:

    Hello,
    How has the bedugging gone? were you able to find the source of the issue?

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