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DAC38J84: DAC38J84 CONFIG73 LINK ASSIGNMENT

Kubilay Savci
Prodigy 70 points
Part Number: DAC38J84


1) What is the meaning of "link" in config73 register of DAC38J84? JESD204 link or 4 output channels of DAC

2)I wish to use only the 2 channels (A-B enabled and C-D disabled) of the DAC. My configuration is LMF=421 and 4 lanes are active on FPGA side which will be routed to channel A and B outputs. In this case, how should I do the link assigments?

I have come up with two solutions but don't know which is correct?

If I assume what you mean by link is JESD204 link, then;

lane0 link sel: 00 JESD204 Link0
lane1 link sel: 00 JESD204 Link0
lane2 link sel: 00 JESD204 Link0
lane3 link sel: 00 JESD204 Link0
lane4 link sel: 01 JESD204 Link1
lane5 link sel: 01 JESD204 Link1
lane6 link sel: 01 JESD204 Link1
lane7 link sel: 01 JESD204 Link1

If I assume what you mean by link is output channels, then;

lane0 link sel: 00 chA
lane1 link sel: 00 chA
lane2 link sel: 01 chB
lane3 link sel: 01 chB
lane4 link sel: 10 chC
lane5 link sel: 10 chC
lane6 link sel: 11 chD
lane7 link sel: 11 chD

  • 0
    TI__Guru* 80125 points

    Hello,

    1. The JESD204B standard defines multi-link within a converter, which each link can have independent hand-shaking of the link establishment on its own without affecting one another. Each link is formed by a single to multiple lanes, and can address to a single DAC or multiple DAC depending on the LMFS setting. 

    The DAC38j84 family of devices can support up to 2 independent links, with link0 handled by handshaking signal of SYNC_N_AB, and link1 handled by handshaking signal of SYNC_N_CD. You can aggregate the lanes necessary for DAC-A/B into link 0 through the assignment of the 0x49 register, and also aggregate the lanes necessary for DAC-C/D into link 1 through the assignment of the 0x49 register. Link2 and link3 are not supported since we do not have sufficient SYNC signal for additional link hand-shaking sync request signal. 

    The SYNC request signal is used by the JESD receiver (DAC) to address and request hand-shaking protocols from the ASIC/FPGA JESD transmitter logic devices.

    2. the link assignment depends on how many link you need in your application. In the default EVM GUI and also the TSW14J56 EVM evaluation, we only support single link0 configuration because the FPGA is configured for single link. You can download the DAC38J84 GUI and see how the 0x49 is configured based on the default single link setting.

    Dual link settings are useful for redundancy reasons. If one link is down, the other link will not be affected, and the DACs of the associated link will remain in transmission mode.

    -Kang