ADS8688: short event at the ADC power stage, when interferences are present

Hello,

The primary engineer for this product is out of the office for US holiday but will reply back the week of 11/26.  Until then could you provide a little more information about the short event?  We're guessing the ADS8688 is permanently damaged after the event but can you confirm because of visible damage or shorts between pins?  Does the short appear between AVDD and GND?

The ferrite between the two GNDs could be developing a significant voltage across it during transient immunity testing which may violate some ABS max ratings of the device resulting in the damage.

As mentioned we'll look further into this and will get back with you next week.

Hi Collin,

thanks for your feedback. We wait then till the next week.

Addressing your questions: The ADS8688 was not getting damaged, after reapplying the power it was coming back to operation. The partial short was on the AVDD line.

Kind regards,
Bartosz

Hi Bartosz,

Can you please describe what the short event shows? was the AVDD shorted to GND when the interference was coming from external power generator to the AVDD of ADS8688 device? What's the interference level and frequency? a scope for the interference signal will be helpful to understand. Which ferrite bead(L14,L17 or both) was removed to solve the problem?

Thanks.

Best regards

Dale

Hi Dale,

please see the feedback from customer below:

1. Can you please describe what the short event shows?

External noise (from power grid, when switching the power on, noise similar to burst test) caused the system to enter the state of increased current consumption by AVDD (over 100mA). Large current causes in our system a voltage drop of up to 2V and stops the operation of the ADC block. The power reset fixes the failures and the system continues to operate normally.

2. Was the AVDD shorted to GND when the interference was coming from external power generator to the AVDD of ADS8688 device?

I used internal references. I haven't tested external references.

3. What's the interference level and frequency? A scope for the interference signal will be helpful to understand.

FCLK = 8MHz, read frequency 8kHz. In this period we read all 8 channels.

4. Which ferrite bead(L14,L17 or both) was removed to solve the problem?

Removed only L17 (and shorted it) - this solved the problem.

Hi Bartosz,

1. Thanks for your clarification.

2. I was not asking the reference, the interference means external noise as you said.

3. I was asking the signal level and frequency of interference(external noise as you said)

4. Thanks for your clarification.

Do you mean that +5V_ANA to ADC is dropped to 2V when the external noise caused by switching shows up?

Based on your current information, I think the possible reason is, the absolute maximum range on AIN_nAGND was violated and a latch-up condition was triggered. The signal to  AIN_nAGND should be limited to -300mV to 300mV. To verify it, you can do below tests:

• keep monitoring the voltage difference between AIN_nGND and AGND when switching the external power.
• Install L11 on input channels but short and remove L17, then check if ADC is still working when switching the external power.

Please let me know the result. Thanks.

Best regards

Dale

Hi Dale,

"Do you mean that +5V_ANA to ADC is dropped to 2V when the external noise caused by switching shows up?"

The supply dropped to 2V because current consumption by AVDD (over 100mA) is to high for my power supply. If I supply ADC from stronger power source, then the ADC works but IC becomes very hot.

• "keep monitoring the voltage difference between AIN_nGND and AGND when switching the external power."

I installed L17. Actually the noise between AGND and AIN_nGND exceeds range -300mV to 300mV (my scope is not immune to noise)

• "Install L11 on input channels but short and remove L17, then check if ADC is still working when switching the external power."

ADC is still working after doing that. When I switch external power, ADC enters the state of increased current consumption by AVDD.

"The signal to AIN_nAGND should be limited to -300mV to 300mV. "

I did not know about it. I will change the ADC's PCB circuits.

Hi Bartosz,
Thanks for your information and update. Please refer to the Absolute Maximum Ratings table in page 6 of ADS8688 datasheet to get more information about input limitation for AIN_nP and AIN_nGND.

Best regards
Dale