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ADS1263: SPI Communication with ADS1263 and ATxmega256a3bu
Part Number: ADS1263
We are working on ADS1263 adc which has maximum sampling rate of 38400 SPS as per datasheet.
So, technically we should get number of sample per cycle=Sampling rate/ Input frequency.
E.g. For 10 Hz input sinusoidal signal, sampling rate after setting 38400 SPS, we should get 3840 samples.
But in this condition we are getting 510 samples.
After checking datasheet again we found that conversion latency of Sinc5 filter for 38400 sampling rate (page number 63 Table 17. ADC1 conversion latency).
We also found that new data is available as per this latency only i.e. after
0.207 ms for 38400 SPS.
We would appreciate if you clarify on this, if sampling rate is mentioned 38400, we should get output samples according to it.
What role does the Sinc5 latency plays in getting digitized data?
Welcome to the TI E2E Forums!
The continuous conversion period of the ADS1263 is indeed 1 / [data rate]; however, the first conversion will not appear for 0.207 ms (@ 38.4 kSPS), as you mentioned.
The reason for this is that the SINC5 filter is much like a moving average filter that averages the last five conversion results. If you have already acquired enough data to fill the filter, then the filter will output a new result after each conversion. However, when starting a new conversion the first "settled" result will not appear for 5 conversion periods.
Are you MUXing between channels or running the ADS1262 in pulse convert mode? If you are only sampling a single channel and not restarting conversions or re-configuring conversion registers, you should see more samples.
Best regards,Chris HallApplications Engineer | Precision ADCs
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In reply to Christopher Hall:
I am using continuous conversion mode for single channel (AIN0 and ANI1), and I am reading samples by sending read command for every sample.
When I am checking status byte for every sample for keeping track of new data. But I am observing new data is coming after every 200 us (that equal to latency of sinc5.)
In reply to ASHISH Kayarkar:
How often are you reading data (polling) and are you doing any operations between data reads that might restart the ADC Conversion (for example toggling the START pin or writing to the device registers)?
If not, would you be able to share more details about your ADC clock frequency, SCLK frequency, and how you are programming the ADC registers (i.e. a list of hex values for each register)?
I am reading at a sufficiently high speed so that,if I ignore status byte I am getting 5 repeated samples for 38.4 Ksps.
SCLK is 5 MHz.
I have checked Start pin , it is not toggling.
Here are my registers programming hex codes
5. 0x120000000000 --> For ADC Read
Thank you the comment Christopher .
This resolves my issue.Now I am getting number of samples as expected.
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