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ADS8881: Specs for Sub-sampling

Part Number: ADS8881
Other Parts Discussed in Thread: ADS8471, ADS7279, ADS7854, ADS7042, ADC14L020, ADS4142

Hi, I am thinking of using a ~1MSPS ADC, like ADS8881,  to sub-sample a bandlimited signal around 10 MHz. The mentioned part specifies a -3dB bandwidth at 30 MHz, but apart from this there are no specs at all of the performance at frequencies above Nyquist. This holds for many other TI ADC I checked. How can I get information like SFDR when using your chips in this way?

  • The same question is valid also for chips like ADS8471 and ADS7279. The latter for instance, has SFDR specified only up to 100 kHz, but has a 30 MHz BW.
  • Hello,

    TI does not typically characterize the SAR based converters for under sampling; at these lower input frequencies most customers prefer to use the high speed pipeline converters. The input bandwidth is largely determined by the input sampling capacitor and sample switch resistance, and is useful for determining worst case noise bandwidth of the input signal.

    High performance devices like the ADS8881 use an internal error correction algorithm to determine the lower LSB's of the result. At higher input frequencies, this algorithm breaks down and the AC performance will decrease quite a bit, long before the 3db input BW is reached. For that reason, we do not recommend most higher performance, 16b or greater, SAR adc's for under sampling. You could use the ADS8881, but the performance will be similar to a 12-14b ADC in these conditions.

    Most of TI's mid performance (12b, 14b, and some 16b) SAR ADC's use the more common SAR structure and can be used for under sampling. We do not have an exhaustive list of devices, but a few that are known to work are the ADS7042 and ADS7854. As far as specific performance specs such as SFDR, you would need to measure that in your target system as we do not have any characterization data under these conditions.

    Regards,
    Keith N.
    Precision ADC Applications
  • Thank you very much.

    Going up in speed a bit, can you say anything about a chip like the ADC14L020, would it maintain its specs when sampling above Nyquist?

  • Hello,

    The ADC14L020 is a pipeline converter, but there is no information in the datasheet for input signals above the clock rate, so we would not be able to guarantee specs under these conditions. Also note that for this ADC, the minimum clock frequency is 5MHz; I believe you are wanting to clock(sample) at 1MHz or lower?

    Can you comment on why sub-sampling is desired or needed in your design? You mentioned in your initial post that you were sampling a 10MHz input signal. What is the BW you are trying to capture? Are there any other key specs that you need to meet?

    The ADS4142 may be a better fit; it can be clocked down to 3MHz, and has specifications for undersampling (although not at your lower clock and frequencies). This part will also support direct sampling (up to 65MHz clock/sample rate).

    Regards,
    Keith
  • Hi Keith, Thank you again. Appreciated!

    The application is radio reception. I want to A/D-convert a signal coming out of a 10.7 MHz (or so) ceramic IF filter. With a -3dB bandwidth of 100 kHz and steep stop band attenuation. The initial idea is to mix down the centre to some 150 kHz, and sample at 600 ksps or so, but if I can get rid of oscillator + mixer and instead sub sample with the same or better performance that would be a very interesting option. Price is also an issue here. And a signal at 30 MSPS or so would probably take too much of resources to filter and decimate.

    I'll look at ADS4142, but DDR LVDS only might not be the best for me.

    Regards, Daniel