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ADS131A04: Master mode timing : DRDY timing

Nopphon Detmaneenin
Prodigy 100 points
Part Number: ADS131A04

Hello,

I would like to know the minimum time of the DRDY during high in master mode.

Because I want to know how much time I have before the next data come in.

  • 0
    TI__Guru* 92715 points
    Nopphon,


    I wasn't quite clear on the question, but let me give a two answers and see if one works for you. If you're talking about the amount of time /DRDY is high to indicate the completion of a conversion, this value is 0.5 tmod. It's not pointed out in the timing diagrams, but it is discussed in the Data Ready section on page 43 of the datasheet. The time for tmod is dependent on the ICLK_DIV setting in the CLK2 register.

    If you are asking about the time from the start of a conversion to the falling edge of /DRDY, this is a function of the OSR register to get the data rate. This data rate is shown in Figure 30 of the datasheet. Invert this data rate to get the data period. This time is deterministic and only varies with changes in the external clock and the ICLK_DIV setting to give fmod.

    Again, if this didn't answer your question, please post back and let me know.


    Joseph Wu
  • 0 in reply to Joseph Wu
    Prodigy 100 points

    OK, got the answer from your first answer.

    Thank you.