TLV2553: Output pins not going low

Hi Brian,

Thanks for your post!

If you look at table 6.5 of the datasheet, you will see that the Low-level output voltage is either 0.1V or 0.4V depending on your operating conditions.

However, from your screenshot it looks like the low level is sitting around 4V - much higher than the max spec in the datasheet.

This could be related to the output drive strength of the device, but I will have to do some additional digging to find a solution for this.

Testing the part independently would be the best way to confirm if it's a system level or device level issue, but I'm assuming this is not easily possible for you. Give me some time and I'll see what I can do.

Hi Brian,

This almost looks like a bus contention issue. Is the level shifter enabled and are the FPGA pins configured as inputs?

Thanks for the replies.

The level shifter pin is high (thereby releasing the inhibit) and the FPGA pins are definitely setup as inputs.
The problem is the signals between U25 and U27 however, so I'm not sure if the status of the FPGA pins is relevant.

As Alex alludes to, the output pins (Y3 and Y4) are always high, as I would expect given that the input side signals never drop below the low voltage threshold. This is pretty much exactly the problem: the input pins effectively never go low, even though the ADC logic wants them to be, so the output pins are always high.

No testing the part independently unfortunately isn't really possible.
Please let me know what you find.
I was thinking of adding a pull down of 100R or so on each signal line and seeing what that does.

Hi Brian,

If I'm not mistaken, U27 is a bi-directional level shifter. If the Y side pins are (being driven) high (or configured as outputs), the A side won't be able to drive them below your VCCA. What are the clock, DIN and /CS lines tied to? Do they behave correctly?

Yes it is bidirectional, but there is no pin that selects the direction.
After continuing to look at this on my own, the problem is probably the voltage levels. VCCA must actually be lower then VCCY and I'm violating this rule. I will have to revise.