DAC7811: Sample Rate vs. SPI Clock

Hi Martin,

Population of the parametric search tool is not the most intelligent system - it does not necessarily "cascade" specifications and their implications on one another or perform any sophisticated study of the implications of the timing diagrams. Essentially the sample rate shown in the table is purely drawing upon the settling time specification in the datasheet in that 1/(0.2us) = 5MHz.

Meanwhile, your observations are true. When one takes into consideration the SPI frame requirements along with the setup and hold times with respect to SYNC rising and falling edges, plus the minimum SYNC high time the actual throughput the SPI interface limits the device to is closer to just under 3MSPS.

In order to really push precision DAC throughput to the limit we have to consider parallel interfaces with the current portfolio, though there are some other concepts to aid with this in the roadmap which we can discuss offline.

Can you share the customer requirements? Is supporting a parallel interface a possibility? If they're considering speeds on this magnitude I would imagine we're looking to an FPGA versus MCU / DSP so parallel may be an option.