DAC9881: Power-Supply Sequence

Itabi-san,

I believe the reason behind the power-supply sequence comments in the datasheet are due to the AVDD supply being the input to the internal POR comparator. If IOVDD were to come up first, the digital interface would not yet have been initialized by the POR which could lead to device corruption. Similarly the VREF ESD structure on the positive side are connected to AVDD, so if VREF were applied before AVDD the ESD cell would be forward biased and conduct to AVDD, which either has the possibility of damaging the ESD cell or effectively back-powering AVDD which also could corrupt the POR sequence.

If all of the supplies come up at the same time then I don't think there should be any problems or risk to damage.

I think a good way to validate would be to request an oscilloscope capture of the supplies ramping from the customer. If there is something unexpected happening, we should be able to make some observation from this capture.

Duke-san,

Thank you for your reply.

What is the meaning of "device corruption" ?
Is it destruction of device?

Or is it that it doesn't work right?

Best regards,
itabi

Itabi-san,

Sorry for the ambiguity.

Essentially the POR circuit is critical for triggering a read-sequence for internal memory which contains many important parameters for configuring the device at start-up. This can include, but is not limited to, trim coefficients, default register contents, and in some cases even the resolution settings for the device.

In such a case, the device would not be permanently damaged - however it may exhibit some of these unexpected properties.

Duke-san,

Thank you for your detailed explanation.

POR and hardware reset are same behavior, aren't they?

Best regards,
itabi

Itabi-san,

Not necessarily. The precise functionality varies from device to device. Sometimes Engineers will refer to a HW or SW reset which performs the complete POR either directly as a POR or as a "deep reset". In many devices the HW/SW reset simply restore the internal registers to their default values, however will not trip the complete reload of the internal memory I mentioned in my last post.

As it turns out, reviewing some of my notes, I believe for the DAC9881 the HW reset does trigger the full POR or "deep reset", but I will confirm.

Itabi-san,

I am close to having an answer to confirm this. Just need one more look with the design engineer.

Duke-san,

Thank you for your in-depth confirmation.
We'll have the reset pulse width to be at least 1us.

Best regards,
itabi