DAC81416EVM: About the DAC operation modes

Jianxiong Zhang

Part Number: DAC81416EVM

Hello,

We have a DAC81416EVM board and I have some questions about how to use it:

1. I have read the Spec of DAC81416(SLASEO0-JULY 2018). There some descriptions about the operation regarding register bits and device pins like:

on page 16, or

on page 18 etc.

The question is: Is the trigger signal determined by the OR-logic of register bit and the device pin? i.e. if the LDAC pin is tied to 0 (active) then the register bit LDAC in TRIGGER Register takes no effect. If I want to use software triggering only, then the LDAC pin must tied to 1 (inactive), is it correct?

2. on page 18 in the spec, the toggle mode is described. What are the differences between toggle mode 0, 1, and 2? According to the spec. only one of them can be set at a time, right?

3. In differential mode (according to the description on page 18), which DAC data register should be written? the positive one or the negative one?

4. There are three type of power-down defined in the spec: device power-down on page 25, internal reference power-down on page 26, and the channel power-down on page 30. What is the difference? Is the device power-down including the rest two? If so, does it means the device power-down has the highest priority?

Thanks in advance!

Best regards,

over 5 years ago

0 Uttam Sahu over 5 years ago

TI__Genius 14220 points

Hi Jianxiong,

Welcome to E2E and thank you for your query. I can't see the attachments. Please upload them again.

Please find my comments below:

1. You're right. You need to tie LDAC pin HIGH to use software LDAC. When LDAC pin is tied LOW, software LDAC and SYNC_EN bit is ignored
2. There are 3 toggle inputs. You can choose any one for a particular channel
3. In differential mode, the register with the lower number should be written in a pair. For example, for DAC0-1 pair, write to DAC0
4. In power down, there is no priority. They are switches in series. For example, in order to power-up channel 0, you need to disable the device power-down and disable the channel power-down. Reference power-down needs to be disabled when internal reference is used. In case of external reference, you need to enable the reference power-down bit

Hope that answers your question.

Regards,
Uttam Sahu
Applications Engineer, Precision DACs

0 Jianxiong Zhang over 5 years ago in reply to Uttam Sahu

Prodigy 90 points

Hello Uttam,

Thanks for the quick reply!

I have still some comments about question 2 and 4:

2. That means, if we configure toggle mode in the TOGGCONFIG0/1 Register (p.29), then the according channel can be in toggle mode by asserting the appropriate toggle pin or by setting the proper toggle bit in TRIGGER Register (p.32), e.g. if channel 1 and 3 are set to 0x2h (TOGGLE1), then the toggle operation of channel 1 and 3 can be enabled by asserting toggle pin TOGGLE1 or by writing "1" to AB-TOG1 bit in TRIGGER Register. And the pin and bit is OR-logic just the same as the case of LDAC. Is it correct?

4. The internal reference power-down bit is actually a "enable" bit, and independent of the device power-down. On the other hand, if the device is power-down, the channel is also power-down no matter what value are set in the DACPWDWN Register (p. 30). Is it right?

Thank you in advance!

Regards,
Jianxiong

0 Uttam Sahu over 5 years ago in reply to Jianxiong Zhang

TI__Genius 14220 points

Hi Jianxiong,

In order to enter toggle mode, you need to follow a sequence of steps described in section 9.4.1 of the datasheet. The register bits need to be set in the exact order as mentioned.

Regarding the power-down: all power-down bits are independent of each other. As I mentioned, these bits act as switches in series. The device power-down is a common switch while channel power-down bits are specific to their channels. The reference power-down is also a common switch but this is in parallel to external reference input.

Hope that clarifies your doubt.

Regards,
Uttam

0 Jianxiong Zhang over 5 years ago in reply to Uttam Sahu

Prodigy 90 points

Hi Uttam,

Thanks for the reply.

The power-down question is asked because of the functional block diagram in the Spec. on p.15. There is a module called "Power Down Logic" in the Figure. Does it refer to the channel power down? According to this diagram, if we power-down the DAC channels, we can read/write registers without any problem. But according to the application example in the spec, if we power-down the device, we can still read/write the registers. What does device power-down really do? Does it just shut down the power supply for all the DACs?

And I have some further questions:

5. The register fieleds of the DAC RANGE Register described on p. 31 in the spec are denoted as DACa/b/c/d-RANGE[3:0] whereas in the rest of the spec. the DAC channel are denoted as DAC0/1/2... etc. Which one is DAC0? Is it DACa at address 0x0Ah?

6. The first line of the pseudocode of the application example provided in the spec(p.35) is "WRITE SPICONFIG, 0x0024" and the comment for that is "Power-on Device, Disable Soft-toggle". But if we check the layout of the SPICONFIG register on p.25, the bit 5 DEV-PWDWN here is set to 1, which means Power-off Device accroding to the description in Table 9. Which one is correct, the code or the table?

Thank you in advance!

Regards,

Jianxiong

0 Uttam Sahu over 5 years ago in reply to Jianxiong Zhang

TI__Genius 14220 points

Hi Jianxiong,

Apologies for the delay.

The power-down logic works on the output amplifier.

When the device is powered down, all amplifiers are cutoff from the output and a 10k resistor is connected from each DAC output to ground.

When the device is powered-up but individual channels are powered-down, the same behavior is seen for individual amplifiers.

When a channel is powered-up, the 10k pull-down is cut-off and the amplifier is connected to the output.

5. This is a typo: DACa-RANGE corresponds to 15, 11, 7, or 3 depending on DACRANGE0, DACRANGE1, DACRANGE2, and DACRANGE3, respectively. See Table 19

6. Looks like there is some error with the datasheet translation or you might be looking at an old datasheet. You can look at the latest one at: www.ti.com/.../dac81416.pdf

The SPICONFIG should be set to 0x0A84. Always refer to the register map in case of doubt.

Hope that answers your questions.

Regards,
Uttam

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DAC81416EVM: About the DAC operation modes