TINA/Spice/ADC12DL3200: SYSREF processing activity

Hi Jim,

thanks for your details.

I've prepared two documents:

- the first document is a descriprion of the board and the method used to sync the data;
- the second document is the list of the command used to configure the ADC at the power on.

I've problems to understand the way to attach these file. Can you help me?

Thanks in advance.

Best Regards.

Daniele

Hi Jim, I've discovered another misunderstanding. Reading the datasheet, I've saw that in my ADC configuration

the data sample are aligned following A,C,B,D buses and not A,B,C,D: see the figure 7. Is it correct?

Best Regards,
Daniele

Hi Jim,

do you have any news for the last two messages?

I'm looking forward to hearing from you.

Regards,
Daniele

ADC_CONF_V10.pdfCONF_SINGLE_ADC.TXT

Hi Jim,

ok for the Figure 7.

Do you have any news for the files attached?

I'm looking forward to hearing from you.

Best Regards,
Daniele

Hi Daniele

I reviewed your settings and the additional information regarding your system and have a few questions:

• When you "send a SYS_REF signal and Verify the SYS_REF eye" how many times does SYSREF toggle from low to high? If it is only 1 time currently, try sending it 3 times in succession (or more) and then reading the SYSREF_POS register. That should give the most consistent results.
• When you adjust the SYS_REF delay for one of the ADCs, what is the timing step of the TAP adjustment?
• Can you confirm the ADC1_CLK_P/ADC1_CLK_N (and similar clock signals for ADC2) are AC-coupled to the ADC clock inputs to allow the proper common mode voltage at the CLK inputs?
• Can you check the common mode of the SYS+/SYS- signals applied to the ADCs? I know you are using the SY89327 ECL driver and the DC-coupled LVPECL SYSREF termination mode. I just want to see what voltage that gives at the ADC SYSREF inputs?
• In your register settings file, you said the values written to register 029 are first 2 and then 6. Did you mean to say 0x20h and 0x60h? These are the correct values. Writing 2d and 6d (0x02h and 0x06h) would not give the expected results.

I hope this is helpful.

Best regards,

Jim B

Hi Jim,

I'm not resolved the issue. Below  there are your questions and my answers

• When you "send a SYS_REF signal and Verify the SYS_REF eye" how many times does SYSREF toggle from low to high? If it is only 1 time currently, try sending it 3 times in succession (or more) and then reading the SYSREF_POS register. That should give the most consistent results. I usually send not a single impulse but a signal that is normaly low and when high, it's high for 16 or 32 clock cycles. 
• When you adjust the SYS_REF delay for one of the ADCs, what is the timing step of the TAP adjustment? The TAP time step is about 5 ps.

• Can you confirm the ADC1_CLK_P/ADC1_CLK_N (and similar clock signals for ADC2) are AC-coupled to the ADC clock inputs to allow the proper common mode voltage at the CLK inputs? Yes it is.
• Can you check the common mode of the SYS+/SYS- signals applied to the ADCs? I know you are using the SY89327 ECL driver and the DC-coupled LVPECL SYSREF termination mode. I just want to see what voltage that gives at the ADC SYSREF inputs? I will try in the next days.
• In your register settings file, you said the values written to register 029 are first 2 and then 6. Did you mean to say 0x20h and 0x60h? These are the correct values. Writing 2d and 6d (0x02h and 0x06h) would not give the expected results. I write 0x20 and then 0x60 at the start up. Then, when I must write the new delay value I write directly 6XHex where X is the delay measured through the SYSREF_POS registers.

Now I'm working at 4 GHz clock and I've problems to center the SYSREF Windows:

1. I send 10 SYSREF signals (high for 32 clock cycles) and read the three registers SYSREF POS. In this situation, I've observed, in the SYSREF_POS windows, windows of 7 bits (1000001) that is about 500 ps = clock period of 2 GHZz. Then I select the value that I must write in the four 29 registers and I write their values in these registers. When I send another 10 SYSREF signals the SYSREF_POS Windows shift of 1/2 or 3 bits and I must change another time the value in the 29 registers. Why? This process is potentially really heavy. Is it correct?

2. I the SYSREF_POS I've 2/3 complete Windows and four each ADC I can set different values in function of the Windows read. Is the window selected  change for an ADC, I may observe a change in the data allignment of the four ADCs? 

I look forward to hearing from you.

Regards,
Daniele 

Daniele,

I am the lead digital designer for the ADC12DL3200, and I'd like to help resolve your question.

I'm curious about the exact order of your steps.

The REALIGNED bit will not go high unless you clear it BEFORE you apply a shifted SYSREF pulse. If you apply the shifted SYSREF pulse first and then clear REALIGNED, then you will not see REALIGNED=1.

The REALIGNED bit simply goes high if a SYSREF pulse is processed, but it is inconsistent with the previous SYSREF pulse (e.g. the number of ADC clock cycles between the two pulses is not a whole number of LVDS frame periods).

The ALIGNED bit goes high whenever any SYSREF pulse is processed, regardless of whether it is consistent with the previous pulse. It is intended as a confirmation that SYSREF did in fact get received by the ADC.

Double check that your shifted SYSREF pulse is actually shifted enough to trigger a re-alignment (shifting it less than one ADC cycle may not cause any re-alignment).

Also make sure you keep LVDS_EN=1 during your testing. If you program LVDS_EN=0, the internal frame counter is reset and requires a new SYSREF pulse to re-establish its phase with respect to SYSREF.

Let me know how I can help further.

Hi Paul,

thanks for your analysis and suggestions.

First of all, I've measured the SYSREF signal levels and I've observed these levels:

- High = 1.4V;

- Low = 0.9V.

Considering that the SYSREF input is in DC mode (SYSREF_LVPECL_EN=1) , are these levels correct or not?

Second, I don't understand the following phrase:

Try your experiement again, but don't change SYSREF_SEL. Just input some SYSREF pulses, check SYSREF_POS, and then input some more SYSREF pulses and check SYSREF_POS again.

You say that the SYSREF_POS mustn't be change from SYSREF_SEL selection or SYSREF pulses, is it correct?

When the SYSREF is processed (REALIGNED = 1), have the SYSREF_POS registers the same old values?

Usually, LVDS_EN is 1 during the tests.

The SYSREF signal is generated using the REFCLK signal = 31.25 MHz. This REFCLK is also used to generate the 2 GHz ADC clk with a LMX2594 by TI.

The ADC clk and the REFCLK signals have the same phase and consequently the SYSREF signal has the same phase of the ADC clk.

I look forward to hearing from you.

Regards,
Daniele 

I'll double check with the analog design team on the LVPECL voltage levels.

I'll try to restate myself.  The SYSREF_SEL value you write should not influence the SYSREF_POS result you read back. However, something else might be influencing SYSREF_POS.

You said you were observing a change on the SYSREF_POS result after changing SYSREF_SEL. I was trying to propose an experiment to see if your observed change would still occur even if you didn't modify SYSREF_SEL.

SYSREF_POS and REALIGNED are  independent status values.  SYSREF_POS is just telling you about the arrival time of SYSREF with respect to the DEVCLK waveform.  It provides very fine-grained phase information.

REALIGNED is telling you if a SYSREF pulse actually caused the internal frame counter to realign. This occurs if the SYSREF edge is sampled high on the wrong DEVCLK cycle compared to the previous SYSREF edge.

I recommend always reading REALIGNED first, and then only clear it if it returned a 1. This way you never miss any re-alignment events. If you just unconditionally clear it, you could be missing an event.  If you clear REALIGNED, it won't set itself again until you modify SYSREF enough to cause the frame counter to readjust again.

It's possible for SYSREF_POS to change and REALIGNED to stay at 0. It's also possible for REALIGNED to be set, even while SYSREF_POS doesn't change.  It all depends on how much the SYSREF phase changes.

Small phase changes on SYSREF that are within the setup/hold window with respect to DEVCLK will be reflected on the SYSREF_POS result, but will not cause REALIGNED to fire.

Large phase changes on SYSREF that cause it to be sampled by a different DEVCLK cycle (as compared to previous SYSREF pulses) will be reflected by REALIGNED. SYSREF_POS will also reflect the change if it is not a whole number of DEVCLK cycles.

As for the LMX2594, I'm not sure the 2GHz output is deterministically aligned to the 31.25MHz REFCLK input (it might change when the LMX2594 is power cycled or reconfigured).  I suspect this because it has a channel divider to produce the 2GHz output from the VCO. I don't know if there is anything to ensure that the channel divider output is aligned with the reference clock input. I'm not very knowledgeable about the LMX2594. For example, if the channel divider is 5, there may be 5 possible phase differences that can occur between the 2GHz output and the 31.25MHz input.

I checked the voltage levels with the analog team that designed the SYSREF receiver logic. Here is the response:

If I understood well, LVPECL driver is DC coupled to the SYSREF receiver, which has 2x single ended 50 Ohm termination towards GND.

The SYSREF receiver can handle the aforementioned input levels (VIH=1.4V and VIL=0.9V). However, these conditions put the operation of the block above the designed EM limits for 15%. EM wise (which was a challenge) it was designed for slightly lower input common mode.

I hope this helps.

Hi Jim,

in the last two weeks I had problems to do the test.

I think that the next week I will have the time to close the test of RF section and in particular the
experiment suggested by Paul.

I have attached a picture of the RF section of the board under test. You can see only two ADCs and the T&H.

Thank for your support.

Best Regards,
Daniele