This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

ADS41B29EVM: ADS41B29 eval board + FMC-ADC-adapter has LVDS lines reversed (P for N)

Prodigy 230 points

Replies: 4

Views: 196

Part Number: ADS41B29EVM

We have ADS41B29 eval board, using FMC-ADC adapter rev D to connect to Xilinx board. LVDS P on ADC board connects to LVDS N on adapter.

  • Very likely. P and N lines are often swapped for layout routing reasons. FPGA FW can easily flip signals as needed. --RJH
  • In reply to RJ Hopper:

    Yes, but this is not a transceiver so it is a little more than just flipping polarities. The DDR clock is also inverted so a delay will be needed on odd bits to get them realigned with the corresponding even bits.

  • In reply to david royle:

    Hi David,

    I am assuming the ADC is interfacing with the FPGA. If so, the FPGA pin assignment should allow you to invert both the LVDS Data bus and also the LVDS clock to allow basically transparent capture. The layout has to be done with inversion to avoid crossing. I have checked the ADC datasheet and did not locate the LVDS bus inversion capability. This means that you either have to invert the P/M on your FPGA capture card PCB traces or through the FPGA pin assignment

    If you can advise the FPGA that you are using, I can ask around here at TI to see if FPGA pin assignment can allow for the inversion for your particular FPGA.

    -Kang
  • In reply to Kang Hsia:

    Hi David,
    I have not heard back from you on this issue. I will close this post but you may respond back if further support is needed

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.