ADS131A04: ADS131A04

Hello Bushra,

Welcome to our forum and thank you for your post.

There are three clock dividers in the ADS131A04 as well as a range of master clock (fCLKIN) frequency options. You will need to write to the CLK1 register (0Dh) and the CLK2 register (0Eh). CLKIN is divided down to produce the internal clock (fICLK), which is divided further to produce the modulator clock (fMOD). Finally, the OSR (oversampling ratio) sets the final output data rate (fDATA).

128 kSPS is the maximum data rate. You will need to use a 16.384-MHz CLKIN frequency. In the device registers, select the CLKIN/2 setting in the CLK1 register and the ICLK/2 and MOD/32 settings in the CLK2 register (0Eh) to achieve fDATA = 16.384 MHz / 2 / 2 / 32 = 128 kHz.

Best regards,