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Part Number: DAC37J82
My customer needs TI support for configuring the DAC37J82 ASAP.
Below you can see the block diagram of the DAC37J82 in their system.
they will use all the 8 lanes, and per BW needs to operate at ~2Gbps/lane.
DACCLK and SYSREF are configurable as you can from the block diagram (By PLL)
Could you please provide us the parameters for configuring the DAC37J82 and frequencies of DACCLK and SYSREF.
Thanks in advance and regards,
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I will be glad to help. Can you please provide the following information:
1. DAC sample rate. Do you plan on using the DAC PLL? If so, what reference frequency do you plan on using?
2. Interpolation factor.
3. LMFS setting you plan on using.
4. K value.
5. SYSREF frequency.
6. Do you plan on using the NCO? If so, what frequency.
7. DAC input data rate.
8. Will the scrambler be used.
This is required for me to provided you with the proper register settings.
In reply to jim s:
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