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Part Number: ADS54J20
My customer is working on a new design that uses one ADS5409 and one ADS54J20. They are clocking the ADS5409 at 750 MHz and want to also clock the ADS54J20 at 750 MHz. They want to run both ADS54J20 input channels and use 4 JESD lanes back to their FPGA. We'd like to get your feedback on the simplest way to synchronize the two together?
In addition, we also have the following questions:
1. What frequency should we run the SYSREF clock at, and does it need to be phase and/or frequency sync'ed with the CLKINx? If not using decimation mode,
Max SYSREF rate = Sample clock / (K*N), where N = whole integer. I would suggest using K = 20. This would mean the max SYSREF rate = 37.5MHz with N = 1.
SYSREF must be synchronized with the sample clock. This is why we use the LMK04828 device on this EVM. See the attachment for more info regarding the JESD204B standard that this device uses.
2. We noticed that on the EVM reference schematic a multi-output clock synthesizer is used to provide both of these clocks, is it advised to use this technique? Yes.
3. What's the SYNC input used for - should we connect it to our FPGA so that device's receiver can indicate to the ADC that the JESD is sync'ed, is there any relationship needed between the SYSREF and CLKIN clocks, and the SYNC input? See attached document.
The JESD204B interface is much different than a standard LVDS interface and I do not think you will be able to synchronize these two parts properly. I have never seen anyone attempt this before. The data may be synchronized, but the phase will probably be off every time you recycle system power. There is much more information available on line regarding the JESD204B interface and I highly recommend you take a very close look at this.
1072.JESD204B Overview July_2018.pptx
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