ADS42LB69: Synchronization of two ADS42LB69

daniele sassaroli

Part Number: ADS42LB69

Hi,

I've designed a board with two ADS42LB69. The sampling clock is 125 MHz
and this clock is distributed at two ADS42LB69s.

Now I must synchronize the data acquisition from the four ADCs (2xADC in each
ADS42LB69).

Do you have any suggestions?

In the board I've the possibility to stop the sampling clock and then restart
without glitch.

Is it possible to stop the sampling clock of the ADCs without problems?

Do you think that there is a reduction of the ADC performance?

Is there a maximum time for the stop period of the ADC?

I'm looking forward to hearing from you.

Best Regards

over 5 years ago

0 jim s over 5 years ago

TI__Guru* 91947 points

Daniele,

We are looking into this.

Regards,

Jim

0 daniele sassaroli over 5 years ago in reply to jim s

Intellectual 610 points

Hi Jim,

Do you have news?

Regards,
Daniele

0 jim s over 5 years ago in reply to daniele sassaroli

TI__Guru* 91947 points

Daniele,

Your best bet is to use the SYNC input on both parts. The only drawback is you have to use the input clock divider in any mode except for divide by 1 for this to work. The SYNC has no effect when the divider is set to divide by 1. I have asked the designers about the clock turning off and on but have not heard back from them.

Regards,

Jim

0 jim s over 5 years ago in reply to jim s

TI__Guru* 91947 points

Daniele,

If possible, use the same clock for all parts, minimize skew on clock routing, if possible use same power supply. Stopping the clock should not be an issue. There is no max stop time.

Regards,

Jim

0 daniele sassaroli over 5 years ago in reply to jim s

Intellectual 610 points

Hi JIm,

thanks for your support.

Best Regards,
Daniele

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ADS42LB69: Synchronization of two ADS42LB69