ADS62P49: Asking for amplitude of the clock input

HI,

I am using DAC34SH84EVM to provide CLK 250 MHz for the TSW4200-ADC (ADSP62P49).

I am using an Ext CLK 1 GHz at J9 and I got output CLK of 250 MHz at J10 J11. The divided output CLK then is fed to TSW4200-ADC at J19.

In TSW4200-ADC, it is required to be 1.5 Vpp for the Ext CLK at J19, while the amplitude of output CLK (J10) is as low as -5 dBm (which is equivalent to 0.3Vpp).

In my case, I installed R120 and R121. My concern is how I can amplify the amplitude of output CLK at J10 and J11, at least around 1.5Vpp as required.

Is it good just to connect R53 R56 R57 R59 to VCLK to have larger amplitude?