ADS8353: Offset in the middle of transfer function

[FAE] Andrew Wang

Part Number: ADS8353

Hi Team,

My customer is using Vref*2 mode with ADS8353, and applied 10mV per step to check linearity of our ADC.

In the capture data, they found an offset error right in the middle (Vref) cross-over, customer is wondering if this is expected or not?

Is it included in our INL? What might be causing this error? Sorry customer didn't share schematics with us yet.

Thanks!

Andrew

ADS8353 data.xlsx

over 5 years ago

0 Tom Hendrick over 5 years ago

TI__Guru**** 168605 points

Hi Andrew,

Can you provide any of the raw data from the ADS8353 test? Can you tell us what the observed offset voltage is in their setup?

0 [FAE] Andrew Wang over 5 years ago in reply to Tom Hendrick

TI__Genius 10685 points

Hi Tom,

Yes, the raw data was attached. Not sure if you can see it, I re-attach again. Thanks!!

0285.ADS8353 data.xlsx

0 Tom Hendrick over 5 years ago in reply to [FAE] Andrew Wang

TI__Guru**** 168605 points

Hi Andrew,

Thank you for the data, everything seems to be within the datasheet specifications. I've talked to the design team, and they believe this phenomena can happen depending on how the inputs are driven.

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ADS8353: Offset in the middle of transfer function