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ADS4149: SPI pin setting/ High Performance Mode

Part Number: ADS4149

Hi team,

My customer provided some questions regarding SPI setting.

  1. After programming SPI, each SPI set as follows
    Is this correct?
    1. RESET: High
    2. SEN: High
    3. SCLK: Low
    4. SDATA: Low
  2. There are HI PERF MODE 1 and HI PERF MODE 2. 
    In case of Fc=40MHz, Sampling=200Msps, how should they set for these registers?

I look forward to hearing back from you.

Best regards,

Shota Mago

RESET  : High
SEN     : High
SCLK   : Low
SDATA : Low

  • Shota,

    If the customer is using the SPI in serial mode, they must keep RESET low. After power up though, this must either pulse this input from low to high to low, or do a software reset by writing a "1" to bit 1 of address 0x00.

    SEN should be kept High to prevent any accidental writes. SCLK and SDATA can be at either level.

    Have them select HI PERF MODE 1 by writing a "11" to bits 0 and 1 of address 0x03.

    Since Fc is < 230MHz, have them disable HI PERF MODE 2 by writing a "0" to bit 0 of address 0x4A.

    Regards,

    Jim

     

  • Hi Jim-san

    Thanks for your quick reply.
    If the customer doesn't use HI PERF MODE1, what will be affected for measurement result under condition that fc=40MHz,200Msps?

    Best regards,
    Shota Mago
  • Shota,

    HIGH PERF MODE1 improves aperture jitter of ADC by making input clock buffer stronger (by increasing its current by ~3 to 5 mA).

     

    Impact on input frequencies: So you would see its impact mainly on high input signal frequencies where jitter noise dominates overall SNR of ADC.

    For examples, you may see about 1 to 1.5dB improvement in SNR at -1dBFS with a 230MHz IF sampling at 250MSPS.

     

    Impact on sampling frequencies: If the rise and fall time of clock signal is same across sampling frequencies, impact of this MODE should not depend on clock sampling rate. However, it has been seen, especially in case of sine wave clock, that the rise/fall time of clock signal degrades for lower sampling rates which in-turn degrades the aperture jitter of ADC’s clock buffer. Since this MODE makes the input clock buffer stronger, its impact is more visible at lower sampling rates.

     

    In summary, the MODE is the most helpful for high IF/Low sampling clock combination, and its predominant impact is on SNR, may improve HD2 slightly (1dB or 2) as well.

    Regards,

    Jim

  • Hi Jim-san

    Thank you for detail explanation.

    Best regards,
    Shota Mago