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ADS1251: About Synchronization Mode.

Kengo.Y
Guru 11415 points

Part Number: ADS1251
Other Parts Discussed in Thread: ADS1252

Hi team.

Please let me understand how to read the table.

I'd like to use the Synchronization Mode, but I think it does not work in our system.

According to this table,

Does tDRAY indicate that the clock needs to be counted 384times(typ) ?

If it so, the Synchronization mode needs 1536 CLKs, as it states that it need to pull SCKL of high up to 4times.

Is it correct?

Sincerely.

Kengo.

  • 0
    TI__Mastermind 44770 points

    Hi Kengo,

    The /DRDY pin typically serves as an interrupt to an MCU to indicate when the ADS1251 has completed a conversion. The MCU can then go and read the ADC's data using this interrupt, without having to count clocks.

    For synchronization of multiple ADCs, you will either need to provide a timer delay OR count /DRDY falling edges to know when the ADS1251 enters synchronization mode. So for example, if you have two ADS1251 devices and want to synchronize them so that their conversions are aligned in time, you would...

    1. Set the SCLK signal HIGH on both ADCs. NOTE: You may need to program your MCU to control the SCLK pin as a GPIO (and only set it back to the SPI peripheral function after synchronization is complete).

    2. Then wait for at least 5 conversions to complete (but no more than 20). I am recommending one more than the minimum of 4 conversion periods, since you must wait at least 4 conversion periods from when /DRDY goes low; therefore, waiting for 5 /DRDY falling edges ensures that any current conversions finish AND you've waited the minimum 4 conversion periods. How you implement this wait time is up to you...

      1. You may want to count the number of /DRDY interrupts, OR

      2. You may set a timer to wait for at least 5 * 384 * CLK. For example, if your CLK frequency is 8 MHz, then one clock period is 125 ns, and you'd need to wait at least 5 * 384 * 125 ns = 240 us, but no more than 4 times that delay (or 960 us). If you're worried about the accuracy of your timer and CLK, then pick a delay that is somewhere in between those values.

    3. After you have waited for the device to enter synchronization mode, you may now set the SCLK signal LOW on both ADCs. The /DRDY falling edges of both devices should be very well aligned in time now, indicating that the devices are synchronized. Please note that the SCLK signal needs to remain high the entire time, until the the ADS1251 has entered synchronization mode!
       

    To ensure that both ADCs remain in sync you may want to periodically re-synchronize (in the case that each ADC has it's own unique clock source), OR better yet make sure that you share the same CLK signal to both ADCs.

  • 0 in reply to Christopher Hall
    Guru 11415 points
    Hi Chris.
    Thank you so much your answer.
    I understand how it works.

    Could you tell me one more thing.
    Do you have sample code to synchronize?
    I'd like to compare with our waveform.

    Sincerely.
    Kengo.
  • 0 in reply to Kengo.Y
    TI__Mastermind 44770 points

    Hi Kengo,

    Unfortunately, I do not have any example code for the ADS1252; however, since the function calls for creating an interrupt on any given MCU will be unique an example may or may not be all that useful. However, the pseudo-code for a synchronization would look like this...

    Set START pin high
    Delay (set a timer interrupt or count /DRDY interrupts)
    Set START pin low

    ...If it would simpler to just use the MCU's built-in delay function, then perhaps just call that function to implement the delay and set the delay time to something like 480 us (for the 8 MHz clock example given above), so that you wait approximately 10 /DRDY periods.

  • 0 in reply to Christopher Hall
    Guru 11415 points
    Hi Chris.
    Thank you for your kindness reply.
    I understood.
    If I have additional questions, I'll contact you again.

    Sincerely.
    Kengo.