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DAC7760: DAC recommendation for wireless MCUs

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Replies: 10

Views: 699

Part Number: DAC7760

Hello, I'm using TI's Wi-Fi board; CC3220SF-launchxl

I'm using the HTTP Wi-Fi Web server example and I wish to use my MCU to control DAC outputs.

Since the CC3220 MCU does not support DAC, I'm planning to buy a 4-channel DAC from TI.

With the DAC, I'm trying to create

- 4 Bi-phasic pulses (minimum pulse width = 10μs, maximum pulse frequency = 4kHz)

I will try to connect a passive high pass filter on each channel so that I can create a Bi-phasic pulse.

After that, the filtered pulse will be fed to an Op Amp from TI.

- Creating consecutive pulse

I wish a feature that the DAC chip can create outputs for each channel consecutively.

For instance, after creating a pattern (1.66V -> 0 V -> 3.33 V) on channel 0, channel 0's output is fixed to 1.66V and channel 1 creates the same pattern.

Although this can be achieved by adding some code on the firmware side, I was curious whether I can set this type of feature on the DAC.

Considering the pulse conditions (need 4 channels, minimum pulse width = 10μs, maximum pulse frequency = 4kHz)

and the MCU I use (3.3V supply, supports UART, SPI 20MHz max, I2C),

what DAC chip can I use?

-Best Regards, David

  • Hello David,

    DAC7760 is an application specific device targeted toward industrial 4-20mA loops and voltage analog output modules. It sounds to me like you are looking for a more general purpose DAC.

    To my knowledge we do not have a device that could create the steps you require independently of the MCU. I think this will need to be done in firmware.

    Do you have an idea of the resolution and accuracy your application requires? Also, what is the maximum output voltage required?

    Thanks,
    Garrett
  • In reply to Garrett Satterfield:

    Garrett Satterfield

    Do you have an idea of the resolution and accuracy your application requires? Also, what is the maximum output voltage required?

    Hello, Garrett.

    - bit resolution: 10-bit or above. (12-bit is preferred)

    - want to change the output in 10μs or faster; I expect SPI should be used. CC3220SF supports up to 20MHz clock speed max for SPI

    As you see this picture, where the DAC's output was amplified using an Op Amp, the pulse width is 100μs but I need to change it quicker.

    I need to create a 10μs width signal using TI's DAC.

    - I need 4 DAC channels

    - output voltage range: 0 ~ 3.333 V OR -1.66 ~ 1.66 V (curious whether there is a DAC that gives negative voltage so that I don't need to use a high pass filter)

    Since I'm using CC3220SF-launchxl, I wish to 3.3V logic.

    The power consumption doesn't matter for me. I'm gonna connect a power supply.

    If the package is easy for populating on a breadboard, that would be great.

    Thanks for your help. Hope to hear your recommendation, please.

    -Best Regards, David

  • In reply to David__:

    Hello David,

    I have a few recommendations for you to look at. We do have some DACs that support bipolar ranges but they can be more expensive as the support high voltage outputs. Any of these should meet the settling time you require.

    DAC104S085 - 10-bit, 4ch, 6us settling time, VSSOP/WSON

    DAC60504 - 12-bit, 4ch, 5us settling time, QFN

    DAC61408 - 12-bit, 8ch, 12us settling time, QFN, high voltage bipolar output ranges

    I have linked below a reference design and cookbook circuit guide that shows how to design a circuit to convert the unipolar DAC output to bipolar voltage output. These will be helpful if you want to use one of the first two options. Let me know if you have follow up questions.

    http://www.ti.com/lit/an/slaa869/slaa869.pdf

    http://www.ti.com/lit/ug/slau525/slau525.pdf

    Thanks,

    Garrett

  • In reply to Garrett Satterfield:

    Thanks, Garrett.

    Garrett Satterfield
    5us settling time

    Q0. Is settling time equal to Sample/update rate (MSPS)?

    Garrett Satterfield
    DAC60504 - 12-bit, 4ch, 5us settling time, QFN

    I think this will be perfect, except for the packaging.

    Q1. Can DAC60004IPWR (14-TSSOP) be an alternative? I cannot find the difference between two regardless of the packaging.

    Garrett Satterfield

    DAC104S085 - 10-bit, 4ch, 6us settling time, VSSOP/WSON

    DAC60504 - 12-bit, 4ch, 5us settling time, QFN

    DAC61408 - 12-bit, 8ch, 12us settling time, QFN, high voltage bipolar output ranges

    I thought I could do some simulation using TI TINA 9.

    Garrett Satterfield

    I have linked below a reference design and cookbook circuit guide that shows how to design a circuit to convert the unipolar DAC output to bipolar voltage output. These will be helpful if you want to use one of the first two options. Let me know if you have follow up questions.

    http://www.ti.com/lit/an/slaa869/slaa869.pdf

    Thanks for providing me this. However, it is not possible to simulate the aforementioned items.

    Q2. Is there a way to stimulate the schematic from the cookbook?

    My plan was to add OPA462 (±90 V) or OPA552PA (±30 V) instead of OPA188.

    For instance, I need the output range of -27 ~ 27V by combining the DAC and OPA552PA.

    Q3. How should I set the resistors to achieve this?

    Q4. Also, I should I set the reference input? Do I have to connect an external power supply for that?

     

    Q5. I haven't understood the power connection from the cookbook;

    Since CC3220 use 3.3V, I thought I need to connect 3.3V to the VDD pin on DAC60004.

    What should I connect on VDD; 5 or 3.3V?

     

    Q6. Power-on-reset (POR) configuration: Connecting the POR pin to GND powers up all four DACs to zero scale.

    Connecting this pin to VDD powers up all four DACs to midscale.

    When applying SLAA869, where should I connect POR?

    Q7. Or should I add a high pass filter and an Op Amp to amplify the output on each DAC outputs?

    I'm curious what's the advantage of the SLAA869 compared to this method.

    -Best Regards, David

  • In reply to David__:

    Hello David,

    Find my responses to your questions below.

    Q0. Is settling time equal to Sample/update rate (MSPS)?
    A: No, the settling time specified is analog. The overall update rate will be the combination of the digital write time (which is dependent on SCLK) and the settling time of the DAC/Buffer output. Keep in mind the analog settling time changes based on load condition and step size. The datasheet specified it under very specific conditions.

    Q1. Can DAC60004IPWR (14-TSSOP) be an alternative? I cannot find the difference between two regardless of the packaging.
    A: Yes, the specs for DAC60004 are somewhat different and this device does not include an internal reference.

    Q2. Is there a way to stimulate the schematic from the cookbook?
    A: Yes, see the attached TINA files. They use an ideal voltage source for simulation purposes.

    Q3. How should I set the resistors to achieve this?
    A: Based on equations 2 and 3. If your reference is 2.5V select the ratio 27V/2.5V for RFB/RG1. Then use equation 3 to find RG2. It can be helpful to use series resistors if you need to achieve very close to the exact ratios. Alternately you can set the span wider (-28V, 28V) and calibrate.

    Q4. Also, I should I set the reference input? Do I have to connect an external power supply for that?
    A: Yes, for DAC60004 you will need an external reference voltage.

    Q5. What should I connect on VDD; 5 or 3.3V?
    A: Either. It depends on the value of the reference you choose. See the recommended operating conditions in the datasheet.

    Q6. When applying SLAA869, where should I connect POR?
    A: Most likely to VDD so that the startup voltage will be mid-scale which will yield ~0V output. But you could also connect it to GND and have negative full-scale output on start up.

    Q7. Or should I add a high pass filter and an Op Amp to amplify the output on each DAC outputs?
    A: I do not understand what you are describing. In the SLAA869 circuit you are basically doing this but offsetting to allow for bipolar output.

    Thanks,
    Garrett
  • In reply to Garrett Satterfield:

    Thanks, Garrett.

    Garrett Satterfield
    see the attached TINA files.

    I cannot see your attached file. Can you re-upload them, please??

    For this upload, can I request a schematic that has both DAC60504BRTET as the DAC and OPA552 as the Op Amp, please?

    I want all DAC outputs to be bipolar. However, there is only one reference pin. So I wish to see your schematic and solution, please.

    Garrett Satterfield
    Then use equation 3 to find RG2. It can be helpful to use series resistors if you need to achieve very close to the exact ratios. Alternately you can set the span wider (-28V, 28V) and calibrate.

    Curious whether this is possible with the TINA file.

    Also, does TI has an SPI example code for configuring the DAC60504BRTET?

    Garrett Satterfield
    In the SLAA869 circuit you are basically doing this but offsetting to allow for bipolar output

    Regardless of the application note, I mean, we can combine the high pass filter to make a bipolar output, right?

    If I add a high pass filter to the DAC output and amplify it with an Op Amp, I think it is equivalent.

    Compare to this way, what are the advantages of using SLAA869?

    -Best Regards, David

  • In reply to David__:

    Hello David,

    I was referring to the files linked at the end of the cookbook document. They provide some basic simulations but use an ideal voltage source instead of a DAC model. You can modify based on the op amp you are using.

    http://www.ti.com/lit/zip/slac785

    Q: I want all DAC outputs to be bipolar. However, there is only one reference pin. So I wish to see your schematic and solution, please.

    A: It would be the same circuit with an op amp for each channel of the DAC. The reference voltage would be used for each to set the negative full scale.

    Q: Also, does TI has an SPI example code for configuring the DAC60504BRTET?

    A: We do not typically provide sample code as it can vary depending on the MCU you are using. It is fairly straight forward as long as you configure the MCU SPI hardware/software correctly.

    Q: Compare to this way, what are the advantages of using SLAA869?

    A: The advantage of the circuit in the cookbook is that it can create a DC bipolar output. You are correct you can use the DC blocking capacitor as you show, but you will not be able to control the amplitude of the waveform without changing the op amp gain. With the DAC circuit you could control the amplitude/waveshape via software. This may not be needed in your application, in which case you could use the MCU digital outputs with the circuit you show above.

    Thanks,

    Garrett

  • In reply to Garrett Satterfield:

    Hi, Garrett.

    Garrett Satterfield
    You can modify based on the op amp you are using.

    Thanks! Mind if you can take a look before closing this thread? I also want to ask the pin functions as well.

    I'm planning to use DAC60504BRTET from Digikey.

    Garrett Satterfield
    The reference voltage would be used for each to set the negative full scale.

    Hope I understood your words for this.

    Unipolar_BipolarOPA552.TSC

    Q0. For the 2.5V reference, connect them like the above?

    I noticed this instruction, so I added 180nF. Hope I did it in a proper way.

    I didn't notice the DAC output range was 0~2.5V.

    Q1. In order to get this output range, I have to connect 5V to VDD pin? Does this change regarding the GAIN pin?

    Also, if I supply 3.3V to VIO, then I can use SPI in 3.3V level, right?

    GAIN / RSTSEL / REFDIV / LDAC pins are quite confusing to me.

    Q2. I want the DAC's output voltage to be 0 ~ 2.5V (gain = 1). Should I tie GAIN to GND?

    Since both GAIN pin and GAIN register exists, this is making me confusing.

    Q3. If I toggle (VIO 3.3V to GND), will the DAC be reset? "When connected to VIO all four DACs reset to midscale"

    I'm not sure about the term midscale; what is this? Meaning running normally?

    Q4. I want the DAC's reference voltage to be 2.5V. Should I tie REFDIV to GND?

    Or do I just need to write 0 on REF-PWDWN bit?

    I'm glad to see a good simulation result.

    -Best Regards, David

  • In reply to David__:

    Hi David,

    Yes, you correctly understood how to use the reference voltage.

    Q1. In order to get this output range, I have to connect 5V to VDD pin? Does this change regarding the GAIN pin?

    A: No, VDD can range from 2.7 to 5.5V and still use the internal reference and 0-2.5V output range.

    Also, if I supply 3.3V to VIO, then I can use SPI in 3.3V level, right?

    A: Correct.

    RSTSEL - sets the DAC outputs to either zero scale or mid scale after reset. You probably want to tie this to VIO to set to midscale.

    REFDIV - Same as the gain pin it sets the gain setting on power up before registers are writte.

    LDAC - If this pin is held high by the MCU the DAC outputs will not update until it transitions low. Used to update all 4 outputs simultaneously.

    Q2. I want the DAC's output voltage to be 0 ~ 2.5V (gain = 1). Should I tie GAIN to GND?

    Since both GAIN pin and GAIN register exists, this is making me confusing.

    A: The gain pin just sets the initial configuration before writing to the gain register. If you want to use the internal reference for a 0-2.5V output, you should use DIV setting of 2 and gain setting of 2. See table 1 in the datasheet.

    Q3. If I toggle (VIO 3.3V to GND), will the DAC be reset? "When connected to VIO all four DACs reset to midscale"

    A: I'm not sure about the term midscale; what is this? Meaning running normally?

    No, when RSTSEL is connected to VIO when the device is software reset the DAC register will be written to midscale or 1.25V if using the internal reference with settings described above.

    Q4. I want the DAC's reference voltage to be 2.5V. Should I tie REFDIV to GND?

    A: As described above the pins only set the initial configuration. If you want to use 2.5V reference on power up then tie the GAIN pin high and REFDIV high.

    Thanks,

    Garrett

  • In reply to Garrett Satterfield:

    Hello,

    One point I'll add as I was catching up on this thread to take support for this going forward - it appears you have a 180nF capacitor connected to the REF pin for each of the output buffer circuits. It is not necessary to include this capacitor for each circuit. A single 180nF capacitor for the REF pin is sufficient. In fact, there could be some stability risks associated with using 4x.

    Kevin Duke, MGTS
    ADC Product Marketing Engineer

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