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DAC38J84: DAC38J84 spur

HENRY JUNG
Expert 2030 points
Part Number: DAC38J84

 

Dears.

I have a question about DAC38J84 Spur.

Our condition is as follows

Fs=300Mhz
DACCLK = 2400Mhz
Interpolation = 8

Internal PLL used.

Why does SPUR occur?

Please review.

  • 0
    TI__Guru 66054 points

    Henry,

    Please advise the IF/baseband tone frequency from the FPGA and also the NCO setting on the DAC38j84. 

    there are two possible causes:

    1. the tone from the FPGA is greater than +/-120MHz. The interpolation ratio is 8 with Fdac at 2400MHz, fdata at 300MSPS. The interpolation filter limits the bandwidth before interpolation to be less than 80% passband of 300MSPS, or 240MHz total, or +/-120MHz centered at 0Hz. If the tone exceed the interpolation bandwidth, the images will occur (since the inteprolation filter cannot filter out the out of band images).

    2. If NCO is used, the NCO need to be re-initialized again. The easiest way is to do it through SPI through toggle of the SPI sync bit. Toggle SPI from 0 to 1 and set the trigger source of the NCO to be SPI based and recheck the spectrum.

    -Kang