Hi There,
I found intermittent spur at the output of DAC3482. After change Reg_0x00= from 0xF288 to 0xF287, I can remove the spur. Tuning dataly in Reg_0x24 can also solve the issue.
I would like to know the reason. What was improved in this case by Reg_0x00 and Reg_0x24?
Thanks.
Hello Di Wang,
Most likely there are some setup/hold time violations between your FPGA/ASIC to DAC3482 LVDS bus data interface. You will need to ensure good setup/hold time between the LVDS data and also the LVDS dataclk (DDR) to ensure there are no bit errors among the interface. One good way to adjust the data interface setup/hodl time is the 0x24 register.
Changing the 0x00 from 0xF288 to 0xF287 also changes the syncing of the internal clock divider. You may refer to the following app note for detail:
http://www.ti.com/lit/an/slaa584/slaa584.pdf
-Kang
