ADCS7476: ADCS7476 data

Hello,

I see why this can be confusing.

Assuming that after falling edge of CS, the first edge of SCLK is a falling edge; then the expected Z3 is present after the CS falling edge and before first SCLK falling edge. Thus between CS falling edge and first SCLK falling, this would be the time Z3 is present. This time though is usually very short, thus the first leading zero may not be set up in time for a microprocessor or DSP to read it correctly.

This is why the third falling edge of SCLK refers to the third falling edge of SCLK after CS goes low. The SDO data is then outputted on the fourth falling edge of SCLK. On the 12^th falling edge clock, this is when you should see the trailing zeros

IF after CS falling edge, the first SCLK edge is a rising edge; then all four leading zeroes are valid on the first four falling edges of SCLK.

A helpful visual can be using an oscilloscope on the digital communications and using a DC input at full scale. This will visually show the SDO at the beginning and for how many SCLK, followed by 12 high SDO data bits. please share this if you have any concerns.

I think this will be helpful to visually see the SCLK edges and data transitions. The ADCS7476 does not clock out any trailing zeros, only the lesser resolution devices have trailing zeros, and the least significant data bit is valid on the 16th falling edge of SCLK.

Regards

Cynthia

Dear Cynthia,

thanks for your help！

and there have a question：“why when they open the buffer memory the data is from BIT0--BIT11，and close the buffer memory the data is from BIT1--BIT12？”

hope you can give some comments。