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CCS/DAC38RF80: Is there any reference code?

Jerry Hsueh
Expert 2730 points
Part Number: DAC38RF80

Tool/software: Code Composer Studio

Hi TI

We want to develop DAC38RF80, but there are too many registers.           

Is there any reference code that can help us?           

Can it be provided?           

Thanks.

Jerry

  • 0
    TI__Genius 9695 points

    Hi Jerry,

    No, we don't have code available. We do provide a configuration file, which is text based that you have to write code to dump to the device.

    Thanks,

    Eben.

  • 0 in reply to Ebenezer Dwobeng
    Expert 2730 points

    Hi TI

    Can you help provide the following register configuration?

    Thank you.

    Jerry

  • 0 in reply to Jerry Hsueh
    TI__Genius 9695 points

    Hi Jerry,

    Configuration attached.

    Thanks,

    Eben.

    5898p24MSPS_12x_LMF_882_dualDAC_onchip_PLL_Fnco_1GHz.txt 
    DAC38RF8x 
0x00 0x5800
0x01 0x3080
0x02 0xFFFF
0x03 0xFFFF
0x04 0x00FE
0x05 0x0003
0x40A 0x7C03
0x40B 0x0002
0x40C 0xA002
0x40D 0xF000
0x41B 0x0000
0x423 0xFFFF
0x424 0x1001
0x431 0x0400
0x432 0x0508
0x433 0x403C
0x434 0x0000
0x435 0x0018
0x43B 0x9002
0x43C 0x8029
0x43D 0x0088
0x43E 0x0909
0x43F 0x0000
0x10A 0x8610
0x10C 0x2732
0x10D 0x0000
0x10E 0x00FF
0x10F 0xFFFF
0x110 0xFFFF
0x111 0xFFFF
0x117 0x0000
0x119 0x0001
0x11C 0x0000
0x11D 0x0000
0x11E 0xC71C
0x11F 0x1C71
0x120 0x2B67
0x121 0xC71C
0x122 0x1C71
0x123 0x2B67
0x124 0x0030
0x125 0x2600
0x127 0x8888
0x128 0x0330
0x129 0x0000
0x12A 0x0000
0x12B 0x0000
0x12C 0x0000
0x12D 0x1FFF
0x12E 0x1FFF
0x12F 0x0000
0x130 0x0000
0x132 0x0400
0x133 0x0400
0x146 0x0044
0x147 0x190A
0x148 0x31C3
0x14A 0x0F02
0x14B 0x1301
0x14C 0x1303
0x14D 0x0300
0x14E 0x0F0F
0x14F 0x1C60
0x150 0x0000
0x151 0x001F
0x152 0x00FF
0x153 0x0100
0x154 0x8E60
0x15C 0x0002
0x15E 0x0000
0x15F 0x3210
0x160 0x5764
0x164 0x0000
0x165 0x0000
0x166 0x0000
0x167 0x0000
0x168 0x0000
0x169 0x0000
0x16A 0x0000
0x16B 0x0000
0x16C 0x0000
0x16D 0x0000
0x16E 0x0000
0x20A 0x8610
0x20C 0x2732
0x20D 0x0000
0x20E 0x00FF
0x20F 0xFFFF
0x210 0xFFFF
0x211 0xFFFF
0x217 0x0000
0x219 0x0001
0x21C 0x0000
0x21D 0x0000
0x21E 0xC71C
0x21F 0x1C71
0x220 0x2B67
0x221 0xC71C
0x222 0x1C71
0x223 0x2B67
0x224 0x0020
0x225 0x2600
0x227 0x8888
0x228 0x0330
0x229 0x0000
0x22A 0x0000
0x22B 0x0000
0x22C 0x0000
0x22D 0x1FFF
0x22E 0x1FFF
0x22F 0x0000
0x230 0x0000
0x232 0x0400
0x233 0x0400
0x246 0x0044
0x247 0x190A
0x248 0x31C3
0x24A 0xF002
0x24B 0x1301
0x24C 0x1303
0x24D 0x0300
0x24E 0x0F0F
0x24F 0x1C60
0x250 0x0000
0x251 0x001F
0x252 0x00FF
0x253 0x0100
0x254 0x8E60
0x25C 0x0003
0x25E 0x0000
0x25F 0x5764
0x260 0x3210
0x264 0x0000
0x265 0x0000
0x266 0x0000
0x267 0x0000
0x268 0x0000
0x269 0x0000
0x26A 0x0000
0x26B 0x0000
0x26C 0x0000
0x26D 0x0000
0x26E 0x0000

  • 0 in reply to Ebenezer Dwobeng
    Expert 2730 points

    Hi Eben,

    Thank you for your kindly support.

    Use the configuration you provide.            

    1. The chip lose lock when it starts without blowing a fan?   

    2. Registers 0x65, 0x66, 0x67 report errors?

    How to solve it?

    Thanks,

    Jerry

  • 0 in reply to Jerry Hsueh
    TI__Guru 66054 points

    Hi Jerry,

    The DAC PLL may require some tuning of the VCO code. You may refer to the flow chart for tuning code modification for locking of the PLL/VCO across temperature

    For the alarm error, the SERDES to JESD204B RX block has a FIFO in between. The FIFO error indicates that the serdes rate from your FPGA is not matching with the SERDES rate configuration of the DAC. You will need to double check the SERDES.

    You may refer to the attached presentation for another similar device and apply the JESD error debug to the DAC38RF8x family. 

    AFE76xx JESD204B Alarm Training - General.pdf

  • 0 in reply to Jerry Hsueh
    TI__Guru 66054 points

    Hi Jerry,

    The DAC PLL may require some tuning of the VCO code. You may refer to the flow chart for tuning code modification for locking of the PLL/VCO across temperature

    For the alarm error, the SERDES to JESD204B RX block has a FIFO in between. The FIFO error indicates that the serdes rate from your FPGA is not matching with the SERDES rate configuration of the DAC. You will need to double check the SERDES.

    You may refer to the attached presentation for another similar device and apply the JESD error debug to the DAC38RF8x family. 

    7563.AFE76xx JESD204B Alarm Training - General.pdf

  • 0 in reply to Kang Hsia
    Prodigy 40 points

    address 0x33,bit[14:8]，this is the VCO frequency, modify is invalid. Why is VCO frequency associated with PLL locking?

  • 0 in reply to jan joe
    Prodigy 40 points

     Hi Kang,

    Thank you for your reply.

    Below is my register configuration and error report.Not the configuration you gave.My configuration blew the fan when the SERDES PLL would lose its lock.

    Can you help me find the problem in my configuration?

  • 0 in reply to jan joe
    TI__Guru 66054 points

    Jan Joe,

    This is the VCO varactor adjustment to ensure that we center the VCO such that the VCO stays locked across temperature. You have to tunes this to ensure the loop filter voltage (the bias of the VCO) is within range of the error amplifier of the PLL loop such that the PLL can absorb the up/down of the bias change across temperature. Modification is not invalid. You can always adjust it. Please refer to the flow chart and modify VCO code accordingly to the temperature. 

    -Kang

  • 0 in reply to jan joe
    TI__Guru 66054 points

    Hi Joe,

    I recommend that you generate the script based on the DAC38RF8x GUI and refer to the SERDES PLL setting. This is the fastest and best way to double check your settings.

    -Kang

  • 0 in reply to Kang Hsia
    TI__Guru 66054 points

    Hello,

    Just a friendly ping on the debug status. I will close this thread for now since I haven't heard back from you. You can always reply back to inquire further.

    below is a picture regarding VCO capacitor array related to the VCO code inquiry you had earlier. This will help you with your understanding.