Hi
While powering up the ADC as recommended in the datasheet
Step1. ramp 3.0[V] then stable
Step2. ramp 1.15[V] then stable
Step3. ramp 1.9[V] then stable (AVDD and DVDD are from same source and filtered by ferrite)
It appears that the 1.15[V] "power the 1.9[V]" through the ADC i.e. there is a leak from the 1.15[V] to the 1.9[V]
I checked on the demo board from TI and I measured the same behavior.
Is this expected?
In the datasheet it is stated that if the 1.9[V] rises before the 1.15[V] ther emight trouble with the loading of the registers. How could this current leak (if confirmed) could affect this loading?
Thanks
