Original question:
Hi,
Figure 56 shows that mem_serdes_refclk_sel = 1 would bypass the DAC PLL and take the SerDes reference clock directly from the DACCLKP/N pins.
Would you kindly confirm that config59[15] (serdes_clk_sel) = 1 is the value to bypass the DAC PLL?
Hopeful thanks --todd
Hi Todd,
Config59[15] (SERDES_CLK_SEL) = 1 to use the on-chip PLL as SERDES PLL reference source
= 0 for external clock reference
this was confirmed through operation of device through device GUI
