1. The desired frequency is 70 MHz. So we generated 14 MHz inside FPGA and sent to DAC 3283. Channel 1 cosine wave and Channel 2 sine wave using DDS in FPGA (ZYNQ7000) are sent to DAC alternatively.
As mentioned in the datasheet rising edge of the DATA Clock MSB 8 bits and falling edge LSB 8 bits are sent. After Fs/4 mixing we are seeing both 56 (Fs/4)+14 =70 MHz and 56 (Fs/4) -14 = 42 MHz on the spectrum. Is it possible to generate only 70 MHz with the below configuration?
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