Hello,
I would like to ask about interleave bus mode. Assumed no interpolation for making thing simple. I think the operation is roughly below. Is my understand correct?
CLK1 frequency is 2x faster than DAC sampling frequency.
Internally generated two clocks for receiving data input. These clock is 0.5xCLK1 frequency and 180 degree shifted.
Coming data is latched above 0.5xCLK1 frequency clock so interleaving operation can do.
Figure 50, if MUX select B side, we are wondering what data is input in DACA, this timing A side doesn't selected. I guess above operation so previous A data is there.
I am sorry to write complexly. I hope you can understand what I am trying to say.
Best regards,
Toshihiro Watanabe