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ADS54J69: JESD204B resynchronization

Hiroshi Katsunaga
Mastermind 6480 points
Part Number: ADS54J69
Other Parts Discussed in Thread: LMK04821, ADS54J60

Hello,

My customer has a question about ADS54J69.

[Q]

They are evaluating ADS54J69 with Xilinx Kintex7 JESD204B v7.1 Logic Core IP.

Normally JESD204B is linked up normally.

However, sometimes JESD links are intermittently interrupted and it is resynchronize.

In this case, the following errors have been observed :

* RX disparity error from JESD204 PHY

* RX Not In Table from JESD204 PHY

Is this cause ADS54J69 ?

Do you know what caused this error ?

Is there a workaround for this error ?

Best Regards,

Hiroshi Katsunaga

  • 0
    TI__Guru* 91947 points

    Hiroshi,

    What is the ADC sample rate, ADC mode, SYSREF frequency and serdes lane rate used for this interface?

    Have they looked at the serdes lane Eye data?

    Regards,

    Jim

  • 0 in reply to jim s
    Mastermind 6480 points

    Hi Jim,

    Thank you for your fast response.

    Their configurations are as follows.

      * ADC sampling rate = 330MSPS (Input Clock = 660MHz, divide by 2)

      * ADC mode = 40x mode(2 active lanes/device)

      * SYSREF frequency = 1.03125MHz

      * Serdes lane rate = 6.6Gbps

      * K (Number of frames per multiframe) = 5

    They did not look at the serdes lane eye data.

    They are going to try it, but they have not it now.

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Hiroshi Katsunaga
    TI__Guru* 91947 points

    Hiroshi,

    These numbers appear correct. Can you tell me how they are generating the device CLK and SYSREF? Is SYSREF AC or DC coupled? If DC coupled, what is the common mode voltage of this signal? Are the serdes lines AC coupled going to the FPGA?

    Regards,

    Jim

  • 0 in reply to jim s
    Mastermind 6480 points

    Jim,

    I confirmed your questions.

    [Q1]  How they are generating the device CLK and SYSREF?

    [A1] They are generating the device CLK and SYSREF with LMK04821.

            DCLKout0 -> FPGA Device Clock 330MHz

            SDCLKout1 -> FPGA SYSREF 1.03125MHz

            DCLKout2 -> ADC Device Clock 660MHz

            SDCLKout3 -> ADC SYSREF 1.03125MHz

    [Q2] Is SYSREF AC or DC coupled?

    [A2] It is AC coupled.

    [Q3] Are the serdes lines AC coupled going to the FPGA?

    [A3] These are AC coupled.

    [My additional comment]

    I am confirming for RBD value and the delay for each serdes lines.

    I think the delay variation for each serdes lines is absorbed with elastic buffer in JESD204B concept. 

    If K is big value, LMFC frequency will slow and the margin will increase.

    Additionally RBD can adjust the elastic buffer release point.

    They have chosen the K value of 5.

    I think that value is relatively small.

    Also they may not adjust the RBD value.

    How about you ?

    Best Regards,

    Hiroshi Katsunaga

  • 0 in reply to Hiroshi Katsunaga
    TI__Guru* 91947 points

    Hiroshi,

    Why are they not allowed to increase the RBD value? Is this equal to K? That is the max value this can be. Do they turn off SYSREF after the link is established?

    After the link is established , have them write to address 0x54 a data value of 0x30 to ignore the SYSREF input. This is in master page 0x80, The current data sheet does not show this. If there is a random pulse on the output of the SYSREF AC caps that could cause a false SYSREF, the device will ignore this. This register is shown in the latest copy of the ADS54J60 data sheet and will be added to the ADS54J69 in the next release.

    Regards,

    Jim