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ADS1675: Data conversion timing

435521
Prodigy 20 points
Part Number: ADS1675


Hallo.

I am using the ADS1675 with the following settings.
･ FPATH = 1
･ LL_CONFIG = 1
･ DRATE [2: 0] = 011.  DATA RATE = 1000 [kSPS]

The data is sampled at the high timing of DRDY while the START pin is held high.
I want to accurately measure the data conversion time. How many clocks before DYDY became HIGH when the data was converted?

Will the settling time be 116tclk in Table 5 of the data sheet?

Regards.

  • 0
    TI__Mastermind 47950 points

    Hello,

    The first time after START transitions from low-to-high, the delay will be 116tclk, plus some overhead as shown in Figure 38.  However, all following DRDY pulses will occur at 32 tclk's as long as START is held high.

    If START is pulled low and then high, then you will again have the 116tclk delay.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 20 points

    Hello, Keith Nicholas

    Thank you for your answer.
    I understand when DRDY occurs.
    Does A / D convert data (sample hold) every 32 tclk after START transitions from low to high?

    Regards,

  • 0 in reply to 435521
    TI__Mastermind 47950 points

    Hello ,

    The first time after START transitions from low to high, there will be a 116tclk delay plus overhead.  If START remains high after this first delay, then YES, the ADC will convert data (/DRDY will pulse high) every 32 tclk's.

    Regards,
    Keith