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ADS62P49: Issue with the expected output of digital bits

prem dubey
Prodigy 70 points
Part Number: ADS62P49

Hi I am using FMC150 card having ADS62p49 on a Xilinx ZC706 board LPC connector. I have provided 10 MHz input and when i see the samples coming out of ADC on ILA of Xilinx, the digital output is sine wave but the amplitude of sine wave is also sinosuidally varying. My registers are set for CMOS type output with Low Speed enabled as I am sampling at 61MSPS.

The pin layout for FMC150 shows only pins of ADS62p49 as _N and _P  (For ex CH02_N,CH02_P,CH04_N... 7 such pairs) type LVDS configuration but I am using the ADC with LVCMOS Outputs. Can someone suggest how _N and _P are connected with 14 bits of ADC. 

  • 0
    TI__Genius 12780 points

    Hi Prem,

    It sounds as though this design (FMC150 from Abaco) was not intended to be operated in CMOS mode. That's not to say that it cannot be done, but it may require some firmware work in order to look at each individual CMOS pin. Additionally, the FPGA may not be able to support how the bits are routed (voltage banks, P/N pins, etc..). My suggestion is to contact Abaco, and request support directly from them since they are the creators of this product.

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 70 points

    Thanks for the suggestion. Actually I just figured out it was sampling issue with ILA in Xilinx. I reduced the input frequency to 1 MHZ and saw the output of ADC to be all okay. Probably, ILA was running at 30MSPS but adc samples were coming at 61MSPS hence the distortion in output. 

    Still though , once in every two three cycle there is some spikes coming in the adc output. I will check with changing the sampling rate. 

    Thanks again.