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ADC12DJ3200: timestamp input common mode voltage calculation

Part Number: ADC12DJ3200

Hi TI,

This is regarding the previous post :https://e2e.ti.com/support/data-converters/f/73/t/799832?ADC12DJ3200-timestamp-input-common-mode-and-capacitor-before-balun

I have posted this for knowing how to do interfacing of time-stamp inputs of ADC12DJ3200 with virtex-7 FPGA.

In this post  suggested to use MC100LVEP11 buffer between v7 FPGA and ADC12DJ3200 timstamp inputs and also provided a block diagram showing the connections between output of this buffer and timestamp inputs of ADC12DJ3200. The diagram is shown below:

With this connection, Jim suggested that with 50 Ohm(marked red in above image), the common mode output of this buffer will be 0.58v and if we change this 50 Ohm to 75 Ohm , then common mode output of MC100LVEP11 buffer will be in the range of ADC12DJ3200 timestamp inputs common mode requirements(<0.55v).

In datasheet of ADC12DJ3200, it is mentioned that Timestamp inputs needs to biased externally with the recommended common mode voltage whether AC coupled or DC coupled.

Now ,in datasheet of MC100LVEP11, a diagram is given which shows how to do the termination. And they terminate the P and N signals with 50 Ohm resistor to VTT(VTT= VCC-2V) as shown below:

But the diagram which  provided, there is only 50 Ohm resistor at the output of buffer and another 50 Ohm in series which is internal in ADC12DJ3200 timestamp inputs and these 50 Ohm resistors are not connected to any VTT external or internal to ADC12DJ3200.

Then how does common mode voltage is provided to ADC12DJ3200 timestamp inputs?

Also can you guys please tell me which formula is used to calculate the 0.58v common mode output voltage of MC100LVEP11 buffer, if we do connection as per below diagram: 

An early response will be highly appreciated.

 

Thanks,

Lalit