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DAC38RF82: DAC Spur Questions

Jonathan Geronga
Expert 7930 points
Part Number: DAC38RF82

Hi Team,

We have customer inquiries regarding the document "An Efficient Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-Sampling DAC" in the given link below:

1. Figure 6 is described as showing spur suppression (dBc I assume) versus ripple frequency, but the axis is labeled as ripple voltage (mV pk-pk) versus ripple frequency. Is the former information available?

2. Graphs showing spur suppression versus RF output frequency are shown for only three supplies (VDDCLK1, VDDA1, & VDDPLL1). Is there any information on the other clocking and analog supplies? Particularly if some of them are as sensitive to ripple as VDDCLK1. I'm assuming ripple on digital supplies has no effect, as long as it's not very high (>50mV), but confirmation would be nice.

3. How was the DAC configured for these tests (one or two TX, sampling rate, interpolation)?

4. Is there any information on the spurious performance up to 4.5GHz RF output?

let me know if you need more information from the customer.

Thanks!

Jonathan

  • 0
    TI__Guru* 91947 points

    Jonathan,

    We are looking into the questions regarding the document mentioned above. Regarding the spurious performance up to 4.5GHz RF output, the data sheet has many plots showing this. See figures 4-6 for HD2, figures 7-9 for HD3, and figures 10-12 for SFDR. These all go out to 4.5GHz. These were done with 2 TX, Fdac = 8847.36Msps with an interpolation factor of 12.

    Regards,

    Jim

  • 0 in reply to jim s
    TI__Expert 7930 points

    Hi Jim,

    Thank you for your support and for answering some of the questions above.
    We are looking forward to hearing more from the other questions.

    Thanks!

    Jonathan

  • 0 in reply to Jonathan Geronga
    TI__Guru* 91947 points

    Jonathan,

    The person who did the article is no longer with TI. We do not have the answers regarding what mode the part was in when this test was done. I would follow the guidelines per the document regarding which supplies are more sensitive than others. If you do not plan on using the DAC PLL and the output clock divider, there are several supplies mentioned that will not require such a clean power source. As far as the >50mV ripple goes, I would suggest using the same power devices shown in the document. If you decide to use something else, I would suggest the devices have the same performance or better.

    Regards,

    Jim   

  • 0 in reply to jim s
    Prodigy 10 points

    Hi Jim,

    Thanks for the reply. I had one more question; sorry if it's somewhat unrelated to the initial ones. Does TI have a max transient current for the supplies that should be assumed, either a percentage of max steady-state current, or measurements?

    Tom C

  • 0 in reply to Thomas Clinkenbeard
    TI__Guru* 91947 points

    Tom,

    We do not.

    Regards,

    Jim