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AFE5809: Question about CW bandpass filter design in TIDA-01351

Genius 3445 points

Replies: 7

Views: 149

Part Number: AFE5809

hi there, 

we are refering to TI reference design TIDA-01351 for CW doppler Ultrasound.  When I read doc tiducd9b, some questions about its filters design. Hope some TI expert could help discuss.

(1) For High Pass Filter, I think the -3db cut-off freq should be 1/[2π*C1*(Rth+R1)], however, equation (1) on page 9 seems ignored Rth, Not sure why. So the f_HPF = 54HZ , if  take Rth into calculation, shoud be 48HZ. 

(2) Why use 15MHZ for charger kickback filter in eqation (11), page12 ? I thought the freq range should be around ~20KHZ. 15MHZ seems too large, and the ADC sampling rate is 1MHZ at most.

(3) Is it necessary to add an Anti-Alias Filter (AAF) at the input pins of ADC? How should it be desiged under this ultrasound application  condition ? How the cut-off freq. could be determined? design examples would be fine.

(4) The CW DC gain is 10 in this ref design. If we need larger gain for weaker I/Q signals, we can increase R2 value but concern about larger noise caused by larger resistor values. Any suggestions?

Thanks very much.

  • Hello Yi Xiao,

    We have received your inquiry about the TI reference design TIDA-01351 for CW doppler Ultrasound and will get back to you tomorrow.

    Regards

    Praveen

    TI makes no warranties and assumes no liability for applications assistance or customer product design. You are fully responsible for all design decisions and engineering with regard to your products, including decisions relating to application of TI products. By providing technical information, TI does not intend to offer or provide engineering services or advice concerning your designs.

  • In reply to Praveen Aroul:

    Hello Xiao,

    Thank you for your mail.

    Please find my reply as below:

    1. For the high pass filter, you are right, we have missed the addition of Rth in our calculations. We will be updating the design guide soon with this consideration.

    2. Even though the 15MHz looks large, please refer to the document with the link below. It describes, how to calculate the filter values. Based on those calculations, we get a minimum cutoff frequency of 8MHz. So we have chosen higher value as the product of Rflt and Cflt <= 20.6 X 10^-9

    http://www.ti.com/ww/mx/multimedia/webcasts/Analog_Digital_Simple_Steps.pdf

    3. For use of AAF at the input of the ADC, I am enclosing some links which describe why you would need AAF for ADCs. There are some examples also mentioned.

    https://training.ti.com/ti-precision-labs-adcs-aliasing-and-anti-aliasing-filters

    https://training.ti.com/ti-precision-labs-adcs-hands-experiment-aliasing-and-anti-aliasing-filters?cu=1128375

    https://training.ti.com/node/1139106?context%5B0%5D=1139747&context%5B1%5D=1128375&context%5B2%5D=1139106

    4. The implementation of this design was mainly to show low noise signal chain - due to which you should be able to resolve small signals - with higher effective number of bits by the ADC. As the gain increases, the noise would increase and the effective number of bits would reduce. As there is oversampling by almost 50X (for a signal bandwidth of upto 20kHz), you can use digital filtering to get better performance. Many have still been using 16 and 18 bit resolution ADC, but their effective noise floor would be even higher.

    Thanks,

    Ravindra

  • In reply to Ravindra Munvar1:

    Hi Ravindra,

    In section 2.3.1.4.1.4 of this doc, page12

    how did the equation (9) , the principle of "R_FLT > Ro/9" come from?    

    and why the output resistance of THS4551 is 10ohm? Could you please help further explain ? Thanks very much!

  • In reply to Ravindra Munvar1:

    Another question is , in the link (http://www.ti.com/ww/mx/multimedia/webcasts/Analog_Digital_Simple_Steps.pdf) you gives out in my question (2), page10.

    Why it just use external RF and CF, but ignored the Rs1 and C_SH inside the ADC, to calculate τ value , as I marked out with red circles.

    I thought there should consider both  external RC and internal RC.  

    Thanks again.

  • In reply to yi xiao:

    Hi Xiao,

    Thank you for your mail. Let me try to answer your question as below:

    Hope you have studied the document I had sent to you in my mail earlier. http://www.ti.com/ww/mx/multimedia/webcasts/Analog_Digital_Simple_Steps.pdf

    The choice of components should be such that the RC time constant of the RFflt and Cflt should be much lower than the RC time constant of the Rs1 and Csh. That ensures the Vin settles well before the time constant of the Sample and Hold which should reach 1/2 LSB of the maximum number of bits within the acquisition time. If you go through the presentation, you will see that the value of tAQ already considers the Rs1 and Csh.

    Thanks and regards,

    Ravindra Munvar

  • In reply to yi xiao:

    Hi Xiao,

    The answer to your question is in the presentation that I had sent you the link.

    http://www.ti.com/ww/mx/multimedia/webcasts/Analog_Digital_Simple_Steps.pdf

    in slide 16. This is a good design guideline.

    The output impedance of the THS4551 - please refer to Figure 38 in the datasheets of THS4551. You can see that the closed loop differential output impedance of the THS4551 at 15MHz is approximately 10 Ohms. The value has come from here.

    Hope I have answered your query.

    Thanks and regards,

    Ravindra Munvar

  • In reply to Ravindra Munvar1:

    hi Ravindra , thanks for reply. I will discuss these two additional questions with you in this mail. I read through page 1-23 of the doc you sent me. 

     (1) for R_FLT>Ro/9, I am not sure. Some TI guy told me I should look for open-loop output impedance. As in our current project, we use THS4521, that will be figure  43. I may need more time to make this question clear.

    (2) you mentioned in your latest reply that  "The choice of components should be such that the RC time constant of the RFflt and Cflt should be much lower than the RC time constant of the Rs1 and Csh." From the result to see, on the doc you send me , page 22, the final selected R_FLT = 53ohm and C_FLT=1.2nF, its  time constant is much larger than Rs1=50ohm and Csh=48pf of ADS8900B. I am not sure you are correct.

    From my opinion, the critical part is to ensure the time constant of the  "input RC" is much smaller than the t_AQ parameter of ADC. this is naturally ensured by ADC parameter design.

    (a) when there is no external RC filter, as showed in doc page 7-8 , the "input RC " refers to Rs1 and Csh inside ADC; 

    (b) when we add external RC filter, I think "input RC " should be the equivalent circuit of the cascaded R_FLT, C_FLT and Rs1 and Csh because these two stages of RC are not completely independent. But somehow, on doc page 10, the equation direclty uses exteranl RC value to compare with t_AQ. Maybe this is some kind of approximation, as Rs1 and Csh is such a small load comparing with properly selected external RC, and maybe they just can be ignored.

    Hope I've made my points clear. Thanks.

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