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ADS1675: Timinings specs questions

Pierre Lieutaud
Prodigy 230 points
Part Number: ADS1675


Hi,

Question 1:

Refering to table 4 (Low-Latency Data Rates with Single-Cycle Settling Configuration), how will behave the ADC if accidentally, DRATE is set to 100 or 101?

Question 2:

In table 5 and 6, setting time duration is given respectively to LSCLK for high speed mode whereas in low speed mode is given relatively to CLK.

What makes me unconfortable, is that on all figures (48/38/37/36) tsettle always starts on a rising edge of CLK.

In high speed mode, the relation between LSCLK and CLK is not perfectly fixed : tLCKSCLK parameter (13-20ns) on figure 2.

Could you give some more details on the settling time is computed for high speed mode?

Question 3:

In low speed mode, internal generation, is there  a relationship between outgoing SCLK and incoming CLK?

Does the tLCKSCLK given for high speed mode also applies? Or is the delay between both clock different?

Regards,

Pierre

  • 0
    TI__Mastermind 47950 points

    Hello Pierre,

    Question 1:

    The device will not be damaged, but we do not test or verify proper operation under these conditions.  If you were to accidentally configure in this mode, and then reconfigured to a valid state, you would need to pulse the START pin to properly reset the device.

    Question 2:

    When in high speed mode, all serial interface signals are synchronized to the SCLK output, which is generated by the internal PLL.  In high speed mode, the START signal will need to meet the timing relative to the CLK input, but the other timing specifications related to DRDY, DOUT are now relative to SCLK.

    For figures 36/37/38/48, in high speed mode, DRDY timing specifications are relative to SCLK.  These figures show the timing requirements when in low speed mode.  Figures 1 and 2 in the datasheet show the specific timing requirements for High-Speed LVDS.  t-SETTLE will be a fixed number of SCLK period's, plus the delay from CLK to SCLK (t-LCLKSCLK), as defined in Figure 2.

    For example, High-Speed LVDS, Low-Latency, Fast-Response, 4000kSPS (Table 5)

    CLK=32MHz, or 31.25nS period.

    SLCK=96MHz, or 10.42nS period

    t-SETTLE-LL (max) = 229*10.42nS + 20nS (t-LCLKSCLK) = 2405.4nS.

    Question 3:

    We do not directly specify this relationship since data is clocked out of the device relative to SCLK out, which is a delayed version of CLK.  

    You can back calculate the delay since both CLK and SCLK are specified relative to DRDY.

    t-CLKDR = 23nS (min), 30nS (max)

    t-DRSCLK = 2.2nS (min), 4.4nS (max)

    CLK to SCLK Delay = 18.6nS (min), 27.8nS (max)

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 230 points

    Hi Keith,

    Thanks for the answers.

    It's clear now.

    Regards,

    Pierre