ADS8684: Linux sample code

Joel,

The resident expert for the ADS8684 is out of the office, so I thought I'd jump in with an answer. I'm not sure if this will help, but there are some linux drivers that may add to what you've already built. You can find this in the product folder, but I've provided a link below:

I would note that TI did not directly develop this code, so we generally aren't able to support it. Read through it and see if it helps in any way. Other than these examples, I'm not aware of any other example code for this device. Our primary support mentions this in the following post:

Regardless, if you are having problems with the offset and scale for this device, post back and we can continue to discuss that.

Joseph Wu

Hello Joseph,

Thanks for your answer.

"The resident expert for the ADS8684 is out of the office" => I have already read this somewhere in another thread, where are the TI ADS8684/8688 experts ?!

The driver you indicate is the one I'm using and I'm surprised TI host some code they cannot support...

By the way, Linux or not Linux, I'm checking with a logic analyser today, and my ADS8684 always respond "FFFF" when performing a "Manual Channel" request (page 42 of the datasheet). I do not understand why and any help is appreciated.

Regards,

Joel

Hello Joel,

Thanks for your query on E2E. I came back from a business trip last week.

Can you please share your timing plot (/CS, SCLK,SDO and SDI)? I suggest to test with a DC signal or without a signal(floating input) on selected channel, no need to change input range which will be simple for the test. Also, your schematic will be helpful to address the issue.

Thanks&regards,

Dale

Hello Dale,

Thanks for your answer and sorry for the late response, I was in vacations.

All inputs have a fixed voltage actually, I have simply connected inputs to the GND except AIN_0P which is at 0.06V referenced from GND (set with a simple trimmer). I have attached a part of the schematic, it is very simple.

I have also made some screenshots of the signal read with my logic analyzer. This is input 0 "Manual Channel" reading. Total duration between the first falling edge of CS to the second rising edge of CS is about 0.3ms. SPI clock frequency is 4MHz. SPI mode is 1 (CPOL = 0 and CPHA = 1).

I have made 2 zooms to show the logic analyzer software data decoding, "C000" transmitted on MOSI during the first exchange, "FFFF" answered by the ADS8684 on MISO during the second exchange.

As already indicated I do not understand answer FFFF, seems it is a default value for any reason, but I haven't read any related info in the datasheet. Or maybe my SPI setup is wrong ?

Thanks for your help.

Regards,

Joel

Hello Joel,

Thanks for your information.

Firstly, I hope that your SPI_MISO(SDO output from ADC) is connected to MISO(input) on your microcontroller, also your SPI_MOSI(SDI input on ADC) is connected to MOSI(output) on your microcontroller. Please refer to a similar query on E2E forum:

https://e2e.ti.com/support/data-converters/f/73/t/606878?tisearch=e2e-quicksearch&keymatch=0xffff

Secondly,I hope you have measured the voltage on REFIO and REFCAP pins, the voltage on both of them should be 4.096V.

Also, I hope your negative input pins (AIN_0GND,AIN_1GND,AIN_2GND,AIN_3GND) have been connected to GND.

When your input(AIN_xP) is connected to the GND, the conversion code should be around 0x8000. When your input(AIN_xP) is connected to the full scale signal(+10.24V), the conversion code should be around 0xFFFF. Please see transfer function in Figure 69 in datasheet.

With the SPI mode (CPOL=0,CPHA=1),your microcontroller will capture the code on MISO pin at the falling edge of SCLK, your microcontroller should be able to capture it during 10ns after the falling edge of SCLK because the hold time for data is minimum10ns. Please see the highlight in red below. You need to double check and make sure if your SPI can capture during this short time with lower SCLK(4MHz) condition.

Regards,

Dale

Hello Dale,

Sorry for this very long delay and thanks for your help on this.

To answer your points:

- I double checked the wiring, it's correct

- Voltage are both 4.096V

- Negative and also positive input pins all connected to GND at the moment

- You indicate "With the SPI mode (CPOL=0,CPHA=1)", it is also what I have configured

I'm going to change the CPU soon because of other functions required, maybe the problem will disappear but if you have any idea...

Thanks

Joel

Hi Joel,

Below are tests you can check:

• Send continuous SLCK instead of byte mode.
• Check your timing with an oscilloscope (not logic analyzer) to see if your CPU can capture the data during 10ns after the falling edge of SCLK.
• Reduce R201 and R203 to 0ohm or small vluae which may not be the root reason but I would like to keep a small value for connecting them to ground.

Regards,

Dale