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ADS1131: Very high single false readings on SPI output time to time

Part Number: ADS1131

We are designing weight scale AD-conversion with ADS1131.

There is one nasty feature, circuit gives very high single readings to SPI bus time to time.

Stable reading may work several minutes, but fail may happen twice or more in seconds.

 

Averaging don’t work since instability is even more visible.

We did glitch filter for taking out very high transitions,

but then scale don’t react immediately to the change of weight.

Customer don’t accept our reaction delay and we don’t have a good solution.

 

Our speed is 80SPS, PDWN is always ON and no bridge switch on use.

SPI clock cycle is 32us. Clock starts 150us after ready detection, MCU is cortex M3.

 

These scope pictures are just ok, only couple last bits vary ok level.

I haven't succeed to take real error to scope yet. 

 

Br:

Timo Toivola

 

  • Hi Timo,

    I don't see any issues with your schematic or timing.  It would be very helpful to know what is the normal value of output code and what is considered to be a 'very high' output code.  Would this code be considered outside of the scale range?

    Issues that can cause spikes in the results are from EMI/RFI noise sources, reading the data result during the conversion result update period, or not properly sign-extending the binary two's complement conversion result.

    If the MSB of the conversion result is logic high, then the result is negative and what seems like a very large output code may actually be quite small.

    It appears that you are only transmitting 18 SCLKs, so you are not forcing DRDY/DOUT high after each conversion.  Are you using an interrupt method checking for the edge transition from high to low on DRDY/DOUT?  Or are you using a polling method?  Using a polling method without forcing the DRDY/DOUT high can sometimes cause the conversion result to be read out at the wrong time resulting in corrupted data.

    If the spikes are caused from external noise sources, then the noise must be prevented from entering your system.  This may require shielded cables that are properly terminated on entry to the PCB along with some additional filtering components in the analog input signal path.

    Best regards,

    Bob B

  • Hello Bob

    False trig seems to be the case, finally I got error on scope, Picture below.

    Something just after last data bit gives trigger for MCU and new clock period starts.

    This then cause all data bits high and one this kind data will mess averaging.

    Our method is DRDY interrupt with own input pin on MCU.

    We thought that end situation can be according last bit high or low, since chip always take data high before DRDY.

    We added extra clock after data and got data line allways to high position, but still we get ghost interrupts time to time.

    Seems that we need to double check interrupt input every time MCU is triggered and ignore false cases.

    This should be possible now when dataline is high and only static low state is real DRDY case.

    Br: T.Toivola

  • Hi Timo,

    Unfortunately your picture did not come through.  Pictures have to be inserted using the Insert Media icon.  If you are picking up spurious triggers, then yes I would also suggest that you monitor DRDY/DOUT to make sure that it is truly low before proceeding to read the conversion data.

    Best regards,

    Bob B