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DAC43608: I2C Byte Level Data in Master Mode and pin connection verification

Jim Amos1
Prodigy 20 points
Part Number: DAC43608

I'm having a difficult time with this DAC.  I'm successfully sending data to what I believe is the DAC_A Data Register, yet there's no output.  The chip is ACK'ing successfully as my master controller is returning successful transmission status for all data bytes.

The I2C bytes sent in master mode from my controller (100KHz clock) with DAC pin A0 connected to AGND:

Address = 0x48
Command = 0x08

Here's where your documentation gets sketchy (and it has errors as well IMHO)
Specifically the data sheet depicts DACA_DATA to be:

MSDB (b11:b8)
LSDB (b7:b2)

So, for my 8-bit 43608 DAC register (DATA[7:0]) what is the correct alignment within this bit field with an approxiamte half scale DAC output of ~50% (0x80)?
Table 5 says "MSB left aligned", but that could be interpreted as follows:

MSDB (b11) = DATA[7]

-OR-

MSDB (b9) = DATA[7]

I've tried aligning data in both positions and STILL NOTHING.
Just in case I am misconnecting pins, here's how I am current wiring the DAC:

!CLR = +5
VrefIN = +5
AGND = GND
VDD = +5
!LDAC = +5
A0 = GND
SCL = SCL (Photon D1)
SDA = SDA (Photon D0)

Scope or Logic Analyzer captures available if needed (and yes, the I2C lines are pulled up properly).
Sure hope you can assist getting this operational.

Thanks in advance.

  • 0
    TI__Genius 14220 points

    Hi Jim,

    Welcome to E2E and thank you for your query. You need to tie the LDAC to GND or drive it low after every write. There are power-down bits for every channel. Please make sure they are disabled. You can refer to the pseudocode in the application section of the datasheet (page # 32).

    Hope that helps.

    Regards,

    Uttam Sahu

    Applications Engineer, Precision DAC 

  • 0 in reply to Uttam Sahu
    Prodigy 20 points

    I'll try that, thanks...

    Would you also clarify the proper alignment of data in the last 2 data bytes?
    I outlined a case in my previous message and would like your official guidance here

    So, for my 8-bit 43608 DAC register (DATA[7:0]) what is the correct alignment within this bit field with an approxiamte half scale DAC output of ~50% (0x80)?
    Table 5 says "MSB left aligned", but that could be interpreted as follows:

    MSDB (b11) = DATA[7]

    -OR-

    MSDB (b9) = DATA[7]

    Thanks again,

    Jim

  • 0 in reply to Jim Amos1
    TI__Mastermind 46290 points

    Jim,

    The two LSBs in the DACn_DATA register are don't cares, as are the top four MSBs. Data resides in bits 11 through 2. For both 10-bit and 8-bit products, the DAC data is MSB-aligned in this bit 11-2 position. Page 30, Figure 63 does a good job of illustrating this if my text does not make sense.