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ADS54J42: The issue is about 2dB lower when the input frequency is 1/4*fs or 3/4*fs

Mastermind 6300 points

Replies: 11

Views: 119

Part Number: ADS54J42

Hello,

My customer have a question about ADS54J42.

[Q]

They are evaluating ADS54J42 on their board.

The issue is about 2dB lower when the input frequency is 1/4*fs or 3/4*fs.

Their sampling rate is 500MSPS.

The following is the evaluation results.

I think this is due to the interleaving block and the setting.

Do you have a way to avoid this issue ?

Best Regards,

Hiroshi Katsunaga

  • Hi Hiroshi,

    We are taking a look into this, and will be back with you soon.

    Best Regards,

    Dan

  • Guru 54040 points

    Hiroshi,

    This is probably caused by the DC offset correction engine. Download the latest version of the ADS54J60 data sheet (same part as the ADS54J42, just faster) and have the customer follow the instructions in section 9.1.4 in regards to freezing or bypassing the DC offset correction functions and see if this helps them.

    Regards,

    Jim

  • In reply to jim s:

    Hi Jim,

    Thank you for your clear comments.

    OK, I understood your all comments.

    Thank you for your cooperation.

    Best Regards,

    Hiroshi Katsunaga

  • In reply to jim s:

    Hi Jim,

    I'm sorry, We have two additional questions.

    [Q1]

    I read section 9.1.4 in ADS54J60 D/S.

    It is described as follows.

    D/S : The dc offset correction block can correct the dc offset of an individual core up to ±1024 codes.

    Is my understanding correct ?

    * +/- 1024 means 2048 cedes

    * ADS54J42 & ADS54J60 is interleaving ADC with 4 core.

    * The wait time for complete DC offset correction is 1/(fs/4)*2048 ?

    [Q2]

    Is  the Nyquist zone setting related to DC offset correction block ?

    Best Regards,

    Hiroshi Katsunaga

  • Guru 54040 points

    In reply to Hiroshi Katsunaga:

    Hiroshi,

    For question #2,

    The settling time is a function of the bandwidth setting of the DC correction loop.

    If the calibration is being done without external signal, we would ideally set a very low bandwidth so that the DC estimate is not impacted by noise. However a low bandwidth would need a large settling time and hence there is a trade-off between getting a low-noise estimate and settling time.

     

    For one customer, we had recommended a bandwidth of ~10Hz (this corresponds to bandwidth-setting register value of 5). We can use the following formula for settling time –

     

    where B is the bandwidth.

     

    For B=10Hz, this comes to  ~ 80ms. So 100ms should be ok. For the customer mentioned above, we had recommended to wait for 500ms.

     

    Regards,

     

    Jim

  • In reply to jim s:

    Hi Jim,

    Thank you for your fast response.

    Is your answer for question #1 ? If it is yes, then I understood it.

    How about question #2 ?

    They want to know that is there no problem with nyquist enable bit is enabled even if they freeze dc offset correction, for example.

    Best Regards,

    Hiroshi Katsunaga

  • Guru 54040 points

    In reply to Hiroshi Katsunaga:

    Hiroshi,

    There is no problem enabling the Nyquist bit with DC offset correction frozen.

    Jim

  • In reply to jim s:

    Hi Jim,

    Thank you for your reply.

    OK, I understood it.

    Thank you for your cooperation.

    Best Regards,

    Hiroshi Katsunaga

  • In reply to jim s:

    Hi Jim,

    Can I confirm the DC offset freezing function or the DC offset bypass function with EVM ?

    Could you provide the example configuration file ?

    Because I tried it with EVM, but I could not work it properly.

    Best Regards,

    Hiroshi Katsunaga

  • Guru 54040 points

    In reply to Hiroshi Katsunaga:

    Hiroshi,

    Attached are instructions on how to bypass and freeze DC offset correction. This cannot be done with a config file. You will have to use low level commands in the GUI to perform these changes.

    Regards,

    Jim

    ADS54J42_bypass_DC_offset_correction.pptx