ADS54J42: How long does it take to become operational after setting NYQUIST_ZONE ?
Part Number: ADS54J42
My customer have a question about ADS54J42.
They are evaluating ADS54J42 on their board.
The issue is about 2dB lower when the input frequency is 1/4*fs or 3/4*fs.
Their sampling rate is 500MSPS.
The following is the evaluation results.
I think this is due to the interleaving block and the setting.
Do you have a way to avoid this issue ?
We are taking a look into this, and will be back with you soon.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
This is probably caused by the DC offset correction engine. Download the latest version of the ADS54J60 data sheet (same part as the ADS54J42, just faster) and have the customer follow the instructions in section 9.1.4 in regards to freezing or bypassing the DC offset correction functions and see if this helps them.
In reply to jim s:
Thank you for your clear comments.
OK, I understood your all comments.
Thank you for your cooperation.
I'm sorry, We have two additional questions.
I read section 9.1.4 in ADS54J60 D/S.
It is described as follows.
D/S : The dc offset correction block can correct the dc offset of an individual core up to ±1024 codes.
Is my understanding correct ?
* +/- 1024 means 2048 cedes
* ADS54J42 & ADS54J60 is interleaving ADC with 4 core.
* The wait time for complete DC offset correction is 1/(fs/4)*2048 ?
Is the Nyquist zone setting related to DC offset correction block ?
In reply to Hiroshi Katsunaga:
For question #2,
The settling time is a function of the bandwidth setting of the DC correction loop.
If the calibration is being done without external signal, we would ideally set a very low bandwidth so that the DC estimate is not impacted by noise. However a low bandwidth would need a large settling time and hence there is a trade-off between getting a low-noise estimate and settling time.
For one customer, we had recommended a bandwidth of ~10Hz (this corresponds to bandwidth-setting register value of 5). We can use the following formula for settling time –
where B is the bandwidth.
For B=10Hz, this comes to ~ 80ms. So 100ms should be ok. For the customer mentioned above, we had recommended to wait for 500ms.
Thank you for your fast response.
Is your answer for question #1 ? If it is yes, then I understood it.
How about question #2 ?
They want to know that is there no problem with nyquist enable bit is enabled even if they freeze dc offset correction, for example.
There is no problem enabling the Nyquist bit with DC offset correction frozen.
Thank you for your reply.
OK, I understood it.
Can I confirm the DC offset freezing function or the DC offset bypass function with EVM ?
Could you provide the example configuration file ?
Because I tried it with EVM, but I could not work it properly.
Attached are instructions on how to bypass and freeze DC offset correction. This cannot be done with a config file. You will have to use low level commands in the GUI to perform these changes.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.