ADC12J1600: ADC12J1600 to TSW14J10 Timed Out Error on HSDC Pro

Hey Jim, 

Thank you very much for the response.

I implemented the corrections that you had proposed and I am now receiving a DDR to file error. I have attached a document detailing every step along the way. 

Could you please let me know how to resolve this? 

ppt for TI.pptx

Vishal,

You are running the wrong version of the ADC GUI. Go to the ADC12J1600EVM product folder on the TI website and download the GUI from here. When the GUI opens, it should report version v1.3.1.

Regards,

Jim

Hey Jim,

Thank you for the quick response. I had the same issue from the below post. So, installed the ADC GUI linked here.

FTDI connection is established with this GUI but i have the "DDR to File" error from the previous post.

https://e2e.ti.com/support/data-converters/f/73/t/727921?tisearch=e2e-sitesearch&keymatch=ADC12J1600%252525252520gui

Vishal,

On the topside of the ADC board, what device is populated for U4? If this is a TRF3765, you may be using the wrong GUI.

Regards,

Jim

Hi Jim, thanks for the prompt response.

The U4 is populated by TRF3765. Could you please share the link of the correct GUI I can use to capture the output?

Thanks in advance.

FTDI cfg.iniVishal,

Download the GUI from the ADC12J4000EVM product folder and use this one. After the GUI is installed, replace the file called "FTDI cfg.ini" in the directory C:\Program Files (x86)\Texas Instruments\ADC12J4000EVM GUI A with the attached file and give this a try. 

Regards,

Jim

Hi Jim,

Still get the same error with 4000EVM GUI A after changing the config file as below.

The Model Number on my EVM is ADC12XXXXEVM A, with a tick on ADC12J1600.

I had gotten the FTDI to work by using the installer attached in 

Please let me know how to proceed from here. Thanks in advance.

.

3480.ADC12J1600_INT_CLK_DEC_4_P54_KC705.pptxVishal,

I had two settings incorrect. Please use 0x08 for address 0x100 and 0x04 for address 0x110 in the LMK settings. See updated attached document.

Regards,

Jim

Hey Jim,

Thank you very much for the reply.

We tried the settings that you had sent us but we continue to get the same DDR to file error. Is there any other source from which this problem could potentially occur (hardware and/or software)?  

In the PPT that you had sent, the FPGA used was VC707 while we are using KC705. Is there any change in the settings when we use one instead of the other?

Regards,

Vishal

Vishal,

I tried this with a KC705 and got it working today. Not sure what your issues could be. As a sanity check, after you program the ADC, give it an IF at 500MHz @  2dBm. You should see two over range LED's turn on. Slowly lower the amplitude of this input until both turn off. I think this will be around -5dBm. This is a good test to verify the ADC board is working properly. What is the status of the eight status LED's on the KC705? Three of them should be blinking (5,6,7) and two should be on (1 and 3).

Regards,

Jim

Vishal,

Are you still having issues with this?

Regards,

Jim

Hey Jim,

Please let me know if there is something else i should be fixing to get this working.

Regards,

Vishal

Vishal,

Did you perform the ADC test I mentioned in an earlier post? From the last screen shot you show of HSDC Pro, it appears the GUI is set to continuous capture mode. Please set this back to single capture mode.

Regards,

Jim 

Hey Jim,

I got caught up with something and could not update you here.

Initially, we had our Overrange LEDs on but on reducing the amplitude, we were able to get it off. 

On the KC705, we have LEDs 5,6,7 blinking and the LEDs 2 and 3 are on and the others are off. Could you let us know what the error now could be because we are now experiencing a "Start ADC to DDR Timed Out Error. We have attached the pictures of eveything as well for your reference. 

Please let us know how we can have this resolved. 

Thank you very much Jim.

Vishal

Vishal,

I am not sure what to tell you. Everything looks correct. Either there is some issue with the ADC board or the Xilinx board. If you would like, I can swap your ADC board with mine. Please send me your email and we can go over the details if you like.

The option is to get Chipscope running and verify you are getting proper data sent across all four lanes.

Regards,

Jim

Hi, Jim

The connection works now, thanks so much for your consistent help.

Could we ask you another question? If we want to send the data onto FPGA, should we also need to configure jesd204B on FPGA? And how should we edit the XDC file for FPGA?

Best,

Haotian.

Haotian,

This firmware was mostly done by Xilinx.See if this document that was provided by Xilinx helps.

Regards,

Jim

3323.JESD204_TI_reference_design.pdf

Hi, Jim

Thanks for your reply. I'll check this file. Another thing is, I noticed in the slides you sent to us, there're several peaks. But for our test, we can only see the noise, the captured data showed no change no matter how we change the frequency of the input signal. So I'm wondering, have you connected the bandpass filter for the ADC, 'cause I noticed in the user guide of ADC12J1600EVM, there are a DC block and bandpass filter connected to the input in the setup. We have only connected the DC block.

Best,

Haotian.

Haotian,

Did you program the NCO? This needs to be set to a value that, when subtracted from the input tone, the result falls in-band with the decimation range shown by HSDC Pro GUI. If sampling at 1600MHz with a decimation of 4, the Nyquist bandwidth is 200MHz. The input tone minus the NCO frequency must be between 0 and 200MHz. The filter is not needed to get an output.

Regards,

Jim

Oh, I see. 'cause we set NCO to the value you used for testing, but our function generator can only generate the sine wave with a maximum frequency of 160MHz. Sorry for this stupid problem... Again, we appreciate so much for your patience and help.

Best,

Haotian.

Hi, Jim

I see our problem now, 'cause we set NCO to the value you used for testing, but our function generator can only generate the sine wave with a maximum frequency of 160MHz.

Again, we really appreciate your patience and help.

Best,

Haotian.

Hi, Jim,

It seems we have some attenuation problems of the output signal, as you can see from the attached pic. The frequency of the input signal is 100MHz, and we set NCO to 0Hz. We're trying to implement differential signals to our input, and the old issue, "DDR to file error" comes back. Do you have any suggestions about how to improve signal integrity? If the differential input signal is necessary, do you know how should we configure the ADC?

Happy holiday.

Best,

Haotian.

I do not think you can use the NCO at 0 Hz. I am checking with the design team regarding this.

Hi, Jim,

Any feedback from the design team regarding our issue?

Best,

Haotian.

Haotian,

Yes, you cannot use the NCO at 0Hz.

Regards,

Jim

Hi, Jim,

So, I'm wondering what's the right way to calculate NCO frequency? As we discussed before, we want to use ADC12J1600 decimated by 4 to sample a chirp signal. 

Best,

Haotian.

Hi, Jim

I'd like to ask my question again to make it more clear. As you can see from my older post, our captured signal experienced severe attenuation. I think it's caused by the NCO setting. So, I'm wondering what's the equation to be used to calculate NCO frequency or how to configure NCO register? As far as I see, the NCO is only dependent on the sampling rate. In our case, it's 1600MSPS in decimation with 4. 

Or, do you have other ideas regarding our signal attenuation?

Best,

Haotian.