ADS54J60: DCLK + SYSREF connection

hi,

we are using ADS54J60 and LMK04821 in our new design.

We want to use LVPECL, and based on the datasheets and LVPECL defaults, the connection would be obvious, and the ADS datasheet is also clear.

Yet, as we are looking at the Eval Kit schematics, e.g. SLAC711.zip for the TSW54J60EVM and SLAR116A.zip for the ADS54JxxEVM, there is a mix of components on the clock lines, which I would like to ask about.

Let us have a look at the ADS54JxxEVM schematics, where the LMK generates a clock to drive the ADC, out of its pins DCLKOUT2,

then the signal goes through the 240R termination and via a series 100nF cap, over to the ADC where it again goes through another series 100nF cap
and a final external 100R termination just before it goes to ADC clock pins.

My questions are:

1) why the dual 100nF series capacitor? Isn’t it a mistake in the schematics or is it there just because the extra EVK option to bring an external clock as well, and we shall not use it, if going just with the LMK?

2) wouldn’t it be better to use a single 10nF on the clock line? Given the clock frequency is 1GHz, the 10nF is what we should put there, could we get a comment here (even the ADS datasheet shows this value).

3) why is there an external 100R termination right next to the ADC, while the ADC datasheet states the 100R is already inside the chip package?
(judging from the Figure 148. Of the SBAS706D - the ADS54J60 datasheet, and the Pin Functions table)

What would be a correct solution then? To follow the ADS device datasheet, or to follow the EVK schematics?

thanks a lot in advance

KR

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