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Part Number: ADS52J90
We want to use multiple ADS52J90 ADCs in parallel as shown in the figure 94 below. TX_TRIG should be a moderately clean signal because of the setup and hold timing requirements imposed on TX_TRIG. The signal integrity of TX_TRIG is uncertain because the design has multiple ADCs branching into several stubs. Do you have any guidance on how we should terminate TX_TRIG for acceptable signal integrity? For example, options might include "no termination" or "source-side termination" or "use a dedicated TX_TRIG signal for each ADC."
Thanks for looking at ADS chips!
TX_Trig accepts 1.8V CMOS logic. 50ohm impedance trace can be run through multiple ADS chips. you can put an optional 50ohm termination resistor at the last ADC. on the FPGA source side, you can plut a 0 ohm resistor in case you need to tune the impedance some.
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In reply to Xiaochen (Sean)Xu:
Thank you Xiaochen for the prompt reply.
1. The "50 ohm termination resistor at the last ADC" will resistor divide the logic signal in half from 1.8V to 0.9V logic. This will not work for 1.8V CMOS logic.
2. The source-side 50 ohms in series will help, but there are other un-terminated stubs on a TX_TRIG trace because of the multiple ADCs.
3. Separate dedicated TX_TRIG[n] lines that each have 50-ohm source-side termination might be the best solution if we can reliably synchronize all the TX_TRIG[n] lines.
Xiaochen, feel free to declare this issue resolved if you don't have any particular reaction to my 3 points above.
In reply to TylerJohnson:
1. no it will not divide down to 0.9V logic. typically FPGA output is low source impedance. we only put a 0ohm resistor as a place holder. The trace impedance of 50ohm will not divide the signal. the 0ohm may be adjusted to 5 to 10ohms based on our experience when ringing is observed.
2. source side won't use 50ohm. 5 to 10ohm is usually used. the TX_Trig is still a slow signal, typically it happens in KHz range. So it shouldn't be an issue.
3. you can use a buffer to do so. while I feel it brings complexity in the design. Khz signal should be OK when you have one FPGA pin to drive mulitple ADCs.
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