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Part Number: ADC08B3000
I have a question about the test pattern output function on adc08b3000.
I want to output test patterns to both D1 and D2 ports. I am debugging using this test pattern output function.
The data sheet contains pattern ”sequence n”” and ”pattern sequence N + 1”.
Does "pattern sequence n" and "pattern sequence N + 1" mean that? (Unfortunately, they are not detailed in the data sheet.)
The data sheet also contains expected values from time T0 to time T15. I think that when reading the capture buffer, test
patterns are output in order from T0 to T15. But, I feel that the test pattern is output randomly.
Every time I read the capture buffer, I feel the test pattern output order is not constant.
If you have any thoughts about these phenomena, please let me know.
Could you tell me if there are any rules for normal output of test patterns?
We are looking into this.
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In reply to jim s:
Thank you very much.
I will wait for your examination results.
In reply to user6238924:
I apologize for the delay, I spoke to the team and the test pattern modes are tested at full speed so I am confident the test pattern won’t have any issues.
The expectation is that the ADC isn’t getting the proper handshaking correct when filling and emptying the capture buffer and/or may not have the control bits set correctly (TPO Test Pattern Output, TPE Two Port Enable). Can you check this please?
The test pattern is created in logic at the ADC output, so the buffer needs to be operated in the same way it would be during normal ADC operation.
If this isn't completely emptying the buffer, or completely filling it, etc. then there can be problems, as the pointers don’t get reset properly.
Therefore, partially filling or emptying of the buffer can result in incorrect results, corrupted data records, etc.
Hopefully this helps.
High Speed Converter Group
Texas Instruments Inc.
In reply to Rob Reeder:
I am very grateful for the support of your staff. Thank you very much.
I felt when I heard your advice.I have been to the operation of the test pattern in the same way as during normal ADC operation.
But, perhaps in the process for our ADC, there may be cases where the buffer is not completely filled.
I'll try to re-examine the process for the ADC.
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