HI:
I am using the ADC ADS54J69 to design our ADC product. And the anlog input end's picture is as bleow:
I met some question:
When we input sine wave signal( it is 10Mhz,1.23Vp-p), after we insert the J701 connector, the input signal is pull down to 0.632Vp-p. It is almost a half of input signal.
I analyze as below:
I disassembly the resistors R709 and R717, the same phenomenone.
But,when we disassembly the resistors R710 and R715, the signal is normal and Vp-p can arrive the 1.15Vp-p.
I want to know this is why. And how we can resolve this question?
thanks
panxiaohong