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ADS9224R: Reading and Writing Registers issue
Part Number: ADS9224R
We're developing an application where we want to sample the ADS9224 at 3MHz. Due to I/O constraints, we can only use a single data line per channel. This means we need to use a clock of 60MHz for clocking the data out of SDO-0/0A and SDO-4/0B. To do this reliably under varying delays, we want to use CRT-S-SDR as the protocol to clock the data out.
I'm running into a very strange problem while trying to get this to work. When using the following configuration, things work as expected:
PROTOCOL_CFG (2h) = 0x20 (select CRT with SDR)CRT_CFG (4h) = 0x01 (select INTCLK for the STROBE output)OUTPUT_DATA_WORD_CFG (5h) = 0x22 (mask READY output, output fixed pattern 0xA55AA55A)
On my logic analyzer, the output looks as follows (note I'm still generating a SCLK even though it is not used), which is exactly how I would expect it. Note I'm running at 1MHz CONVST / 20MHz SCLK for now.
Now when I want to switch to using SCLK as STROBE input in stead of INTCLK, I change a single bit in the configuration:
PROTOCOL_CFG (2h) = 0x20 (select CRT with SDR)CRT_CFG (4h) = 0x00 (select SCLK for the STROBE output)OUTPUT_DATA_WORD_CFG (5h) = 0x22 (mask READY output, output fixed pattern 0xA55AA55A)
However, now it seems the ADS9224R is completely ignoring all of the configuration, and running at its default configuration of using SPI-00-S-SDR, not masking the READY output, and not outputting a fixed pattern:
Even though only a single bit has changed in the configuration. For reference, here are the captures of the configuration step (the first at the top, and the second at the bottom):
Note that I toggle nRST just before the configuration step to clear the existing config. The pulse is 450ns long, and there is 33µs between the nRST pulse and nCS being pulled low to send the configuration. Also note that the configuration clock is very slow, being only 33kHz.
The glitching of the SDOA/SDOB lines at the end is probably an artifact of the fact that these lines become floating (high Z) when nCS is set high.
The total startup sequence looks as follows:
Any ideas on what's going wrong with the configuration? How can changing a single bit in the CRT_CLK_SELECT field make the ADC ignore the configuration completely? Any help would be greatly appreciated.
After increasing the time between the RST toggle and CS going low for configuration from 30µs to 130µs, it now seems to work. This is rather unexpected since the datasheet specifies 1µs wake-up from RST. It seems the 30µs is right on the edge and there is some kind of data dependence in that timing (or I was having some really bad luck with the second configuration).. Still a bit clueless and/or worried that I'm still missing something. Any clues?
EDIT: it appears increasing this time to 130µs isn't a fix. Sometimes the configuration is still completely ignored. What am I doing wrong?
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In reply to Rembrand van Lakwijk1:
Thank you for your post.
I'm not immediately sure what the issue could be. Please allow me to discuss this with the team and get back to you with a reply in a couple days.
Applications Engineer | Precision ADCs
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In reply to Ryan Andrews:
Thanks for your reply. After some more investigation, it turns out there was a glitch in the SCLK line that didn't show up on my logic analyser:
Apparently sometimes this was seen as an extra clock by the ADC. After filtering it out, it seems the configuration issues are gone.
I'm glad you figured it out! Thanks for the update. Let us know if you have additional questions in a new thread if necessary.
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