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  • Resolved

ADS8664: tHT_CKDO value at fSCLK=2MHz

Expert 4410 points
Ryo Akashi

Replies: 3

Views: 85

Part Number: ADS8664

Hello experts,

I got question from customer.
In datasheet "7.6 Timing Requirements: Serial Interface", there is desctiption of tHT_CKDO = 10nsec(TYP).
This test condition is fSAMPLE=500kSPS.
If customer set fSCLK = 2MHz, tHT_CKDO value will change?
They will connect MCU which has requirement of SDO hold time=40nsec.
Thanks and best regards,
Ryo Akashi
Expert 4410 points
Ryo Akashi
  • Mastermind 19985 points
    Dale Li

    Hello Ryo,

    This is a minimum specification to show HOLD time from SCLK falling to previous data valid on SDO, this parameter is independent of SCLK and the sampling rate of ADC, the controller will have to read the data within this time period.

    Thanks&regards,

    Dale

  • Expert 4410 points
    Ryo Akashi

    In reply to Dale Li:

    Hi Dale,

    Thank you for your reply.
    I understand tHT_CKDO is independent of SCLK and sampling rate.
    Let me ask one question.
    SDO hold time is 10nsec and Set up time is 25nsec.
    It means data valid time is total 35nsec (tHT_CKDO + tSU_DOCK). Is it correct?
    Thanks and best regards,
    Ryo Akashi
  • Mastermind 19985 points
    Dale Li

    In reply to Ryo Akashi:

    Hi Ryo,

    Your understanding is correct.

    Thanks&regards,

    Dale

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