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ADS8509: min time for busy signal

Part Number: ADS8509

Dear Technical Support Team,

My system monitors BUSY signal.

I have a question about BUSY.


① Is BUSY signal output any case/ anytime while conversion(tconv) ?

    If BUSY is not output case, could you share the situation?
② What is MIN width about ① case?

    Datasheet tw2 shows max 2.2us only. I guess that it depends on  conversion time.

【Condition】

・Discontinuous clock mode with external DATACLK.

  

Best Regards,

ttd

  • Hello ttd,

    1. Your understanding is correct, BUSY will output low at the falling edge of R/C signal initiated by the controller and it will remain low until the conversion is completed.

    2. We do not have a minimum data for conversion time. Maximum conversion time is usually considered by engineers for a reason to read the conversion data or design front-end driving circuitry.

    Thanks&regards,

    Dale

  • Hi Dale,

    Thank you for your reply. 

    I understand your answer.

    I'd like to monitor the busy signal when communication error occurred.

    Then busy signal is captured by the other clock(not DATACLK) of FPGA. 

    So I need the min of tw2(busy low) and tconv(data for conversion time), however you don't have them.

    Is there the other way to send the communication error(such as conversion error) to FPGA?  

    Best Regards,

    ttd

  • Hi ttd,

    I did not fully understand what you want especially sending conversion error to FPGA. The normal procedure for conversion and data reading is:

    1. Initiate conversion by issuing a R/C signal

    2. Monitor BUSY's rising edge(usually an interrupt is used)

    3. Read data by sending DATACLK to ADC after detect the rising edge of BUSY

    4. If a BUSY signal is not detected during a certain time (the max cycle time is usually used), an error will be considered to have occurred.

    Some design engineers just wait for a certain time (>2.2us max conversion time but < cycle time) instead of monitoring BUSY. 

    Regards,

    Dale

  •  

    Hi Dale,

     

    Thank you for your reply.

     

    I follow your the procedure for my design .

     

    Then the busy is asynchronous signal for FPGA.

    Attached file is the related timing chart(ADC and FPGA).

     ADS8509_BUSY_min.pptx

    For example, when 1MHz of FPGA CLK captures busy, tw2(min) need over 1us. Then FPGA can get busy correctly.

    However if tw2(min) is under 1us, FPGA miss busy signal.

     

    In other words, how much frequency(MHz) does FPGA capture the busy signal correctly?

    I understand you don't have tw2(min).

    However if following example answer(just my thought) matches ADS8509, could you advise it?

    If you have any other idea, could you share it?

     

    ■Example answer①

    FPGA CLK is better over 1MHz(1us) to capture busy correctly.

    Busy signal is always much slower than 1us.

     

    ■Example answer②

    Busy signal always doesn't become pulse like xx ns.

    So FPGA CLK over 1MHz is enough to capture the busy signal correctly.

     

    ■Example answer③

    td1: BUSY from R/C low (20ns-MAX)

    td10:previous data available after CS, R/C low (2us-MIN)

    READING DATA(Page16): The conversion result is available as soon as BUSY returns to high, therefore data always represents the conversion previously completed even when it is read during a conversion.

     

    For the above three point, tw2(busy) must be "between 20ns and 2us" from R/C_"LOW" at least.

     

    ■Example answer④

    tw2(busy) is related to conversion time(tconv) and sampling rate is just 250ksps. 

    So tw2(busy) doesn't became xxns.  FPGA CLK  MHz is enough for capturing the busy without missing busy.

    Best Regards,

    ttd

     

  • Hi ttd,

    The best solution to detect BUSY is using the edge detection in your FPGA instead of level detection, the rising edge from BUSY will indicate the conversion of ADC has completed.

    Also, ADS8681 is a new generation SAR ADC with many features including integrated PGA,ADC driver,high input impedance,1Msps throughput and bipolar direct input and so on, this new ADC is suggested for any new system design.

    Thanks&Regards,

    Dale

  • Hi Dale,

    Thank you for your reply.

    In general, most FPGA requires synchronous by FPGA's internal clock for asynchronous input like busy as attached ppt previous post,

    so  I need to check how to write HDL(verilog or VHDL) for edge detection(maybe it's not normal way).

    By the way, How is the tolerance of internal clock (typ 9MHz)?

    Is busy signal synchronous with internal clock of ADS8509?

    Then I think that busy signal is based on toggling with internal clock(9MHz/110ns)

    Best Regards,

    ttd

  • Hi ttd,

    We do not have data characterized for internal clock's tolerance. Also, unfortunately there is no more information about the busy since this is an old device.

    Thanks&regards,

    Dale

  • Hi Dale,

    Thank you for your reply.

    If busy signal behaves with internal clock(9MHz/110ns),

    I think that FPGA clock should be over faster clock(over 9MHz) than ADC internal clock.

    I understand that you have not more information about busy.

    Best Regards,

    ttd

  • Hi ttd,

    Thanks for understanding.  If possible, please try to use ADS8681 in the future which is a new generation SAR ADC with many features and benefits.

    Regards,

    Dale