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ADS1274: Unable to achieve number of Samples per second

Prodigy 90 points

Replies: 16

Views: 251

Part Number: ADS1274

2 ADCs are used is daisy chained configuration

Mode: Low speed

CLKDIV: 1

Fclk: 4.2MHz

Sclk: 2.56MHz

Data output format: SPI TDM Fixed

These are the settings, but we get only 15 samples per second(for each channel)

DRDY pin is polled for data ready

We need higher SPS, what can be the solution for it ?

  • Hello Santosh,

    Welcome to the TI E2E Community.

    First, with Fclk=4.2MHz, low speed mode and ClockDiv=1, you should be getting an output data rate for each channel of around 1640sps.  Once the part powers up and the DRDY pin starts toggling, you should be able to measure 1640sps on this pin.  (Note that SYNC pin should be held high.)

    With SCLK=2.56MHz (for best performance SCLK should be closer to 1/2*fCLK=2.1MHz, or limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc), you should be able to support around 60 channels when using SPI TDM Fixed mode.

    I suspect you are toggling the SYNC pin after each DRDY.    There is a delay in the output data of 129 output conversion cycles after the SYNC pin has been toggled.  Assuming this is what you are doing, the effective output data rate would be reduced to 1640sps/129=13sps.

    The SYNC pin should only be toggled once after the power supplies have stabilized to synchronize all of the ADS1274's in your system.  After that single SYNC pulse, it should be held high and the ADS1274 will continuously convert data.

    Please let me know if this addresses your problem.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • In reply to Keith Nicholas:

    Hello Keith,

    Thanks for reply.

    after SYNC pin toggled once got following Results at different Fclk.

    Mode: Low speed

    CLKDIV: 1

    Data output format: SPI TDM Fixed

    1)      Fclk - 373 kHz ,SCLK - 328 khz

    144 Samples per Second

     2)     Fclk - 743 kHz ,SCLK - 328 khz

             290 Samples per Second

    3)      Fclk - 1.1 MHZ,SCLK - 1.3 MHZ

             431 Samples per Second

    4)      Fclk - 2.22 MHZ , SCLK - 656 kHz

            746 Samples per Second

     5)    Fclk - 18 MHZ , SCLK - 11 MHZ

           1190 Samples per Second

     6)   Fclk - 21 MHZ , SCLK - 11 MHZ 

          4095 Samples per Second

    Regards,

    Santosh

  • In reply to santosh birari:

    Hi Santosh,

    It looks like you are now getting correct data rates for the first 3 cases.  The output data rate in low speed mode and CLKDIV:1 is Fclk/2560.

    You should be getting higher data rates in cases 4, 5, and 6.  You can confirm by measuring the DRDY frequency. 

    Regards,

    Keith

  • In reply to Keith Nicholas:

    Hello Keith,

    I had confirm with DRDY frequency , it is giving same output as mentioned in
    Can you pleas guide how to improve the sample rate for last 3 cases?

    Regards,

    Santosh

  • In reply to Keith Nicholas:

    Hello Keith,

     Observation i found during Testing 

     ADC Reference  -  1 V

     ADC input voltage - 0.45 V 

     Output Count varies from  0 v to 1.9 v

     Please refer  attached file of ADC output.

     Please guide me to improve our output readings. ADC_Input_Raw_Count.xlsx

    Regards,

    Santosh

  • In reply to santosh birari:

    Hello Santosh,

    Regarding your first question on data rate, as long as Fclk is continuous and stable, the output data rate, and frequency of /DRDY, should be very stable at a frequency of Fclk/2560.

    Possible reasons why /DRDY frequency does not equal Fclk/2560:

    1. Fclk is not stable, or has a high amount of noise.

    2. Fclk is not continuous.

    3. Noise on power supplies or missing bypass capcitors on power supplies.

    Please provide a waveform capture showing Fclk, Sclk, /DRDY, Dout.

    The noise that you see in the readings may be a result of the 'slower' output data rates.  Can you provide the raw ADC readings before conversion to voltage?  

    Please provide a schematic showing the input amplifier and reference circuits.

    Regards,
    Keith

  • In reply to Keith Nicholas:

    Hello Keith,

    Please find the attachment of waveform capture showing Fclk, Sclk, /DRDY, Dout.

    Raw ADC Readings and schematic showing the input amplifier and reference circuits.ADC ckt diag.pdf5808.ADC_Input_Raw_Count.xlsx5808.ADC_Input_Raw_Count.xlsx

  • In reply to santosh birari:

    Hello Santosh,

    I assume your clock is the triangle looking waveform with a frequency of 21.8MHz.  This is likely the cause of the irregular reading rate at the higher frequencies.  This waveform needs to look more like a square wave, and needs to have a peak-to-peak amplitude closer to your IOVDD voltage of 3.3V (it is less than 1Vpp).

    Looking at your schematics, the inputs of the ADC will only accept positive input voltages with respect to ground.  With the ADC negative input tied to ground and a 1V reference, the positive input will only support input voltages from 0V to 1V.  Since the external amplifiers are powered from +/-5V supplies, they could drive the ADC inputs negative, which could cause damage.

    Also, for the reference input, it needs to be driven by a low impedance source similar to the ADC inputs.  Take a look at the ADS1278EVM user's guide for an example of a good ADC input amplifier and reference.

    http://www.ti.com/lit/ug/sbau197a/sbau197a.pdf

    Regards,

    Keith

  • In reply to Keith Nicholas:

    Hello Keith,

    we took care about adc input in hardware which in the of  0v to +1v 

    1st ADC has Volt ref. from ref3125 which is adjust to 1.1 volt and 2nd ADC has Volt ref through adc buffer AD825 

    as  we are not able to improve waveform like square wave at frequency more than  5 MHZ due to some limitations  so we decided to change the mode of adc to get Higher Samples at Low frequency. 

    Mode : High Resolution.

    CLKDIV: 1

    Fclk: 1.1MHZ (image attached)

     ADC_Raw_Count.xlsxSclk: 1.1 MHZ

    Data output format: SPI TDM Fixed

    Samples per Rate is ok as per datasheet,but Adc readings are incorrect.

    please find the attachemet of adc raw readings.

    Regards,

    Aniket

  • In reply to santosh birari:

    Hi Aniket,

    The clock waveform now looks correct.

    You are using two 4 channel ADC's, so a single transfer will consist of 8x24=192 bits.  SCLK will need to be at least 1/2*Fclk, or 550kHz.  However, keeping SCLK at the same frequency as Fclk will be best to transfer the data.

    Please try to capture /DRDY, SCLK, Dout using a 4 channel scope, or trigger on /DRDY and capture both SCLK and DOUT using a dual channel scope with external trigger.

    Regards,
    Keith

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